A Study of Highly Parallel Computing Based on Set-Valued Logic

基于集值逻辑的高度并行计算研究

• 批准号: 08458058
• 负责人: HIGUCHI Tatsuo
• 金额: $ 5.44万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1996
• 资助国家: 日本
• 起止时间: 1996 至 1998
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08458058/
• 关键词: Multiple- Valued Logic; Set- Valued Logic; Logic Circuits; Integrated Circuits; Opto-Electronic Integrated Circuits; Molecular Devices; Molecular Computing

In this project, we investigated a potential of "multiplex computing architectures" (listed below) to address interconnection problems in advanced VLSI systems.1. [Multiple-Valued Logic System] New arithmetic computing architectures using non-binary/high-radix number systems, such as high-radix dividers, a high-radix CORDIC processor, a redundant complex multiplier and reconfigurable arithmetic datapaths, were developed to demonstrate advantages of improving processing latency, circuit complexity, gate count and power consumption. Also, the impact of multiple-valued integrated circuit technology was investigated through experimental fabrication.2. [FDMA/CDMA-Based Computing Architectures] Set-valued logic architectures based on FDMA (Frequency-Division Multiple Access) and CDMA (Code-Division Multiple Access) were investigated. A test chip for ODMA-based set-valued logic was fabricated using current-mode CMOS to demonstrate significant reduction in wiring complexity. Also, flexible control of bit error rate in intra-chip data transmission is possible by controlling the length of M-sequence codes and the degree of multiplexing. This idea was also extended to the design of wire-efficient neural network architectures.3. [Multiwavelength Optical Interconnection] A multiwavelength optical interconnection network for MCM-based parallel processing was proposed and its key device the "wavelength detector" was developed. It was shown that the wavelength detector can discriminate 8 16 wavelengths multiplexed within a waveguide and that this degree of multiplexing makes possible the reduction of network area complexity by the factor of 1/64 - 1/256 in comparison with a single wavelength implementation.4. [Molecular Computing System] A molecular computing architecture using "enzyme transistors" was investigated. The basic function of an enzyme transistor was confirmed experimentally.

在这个项目中，我们研究了“多路计算架构”（如下所列）的潜力，以解决先进的VLSI系统中的互连问题。[多值逻辑系统]开发了使用非二进制/高基数数字系统的新算术计算架构，如高基数除法器，高基数CORDIC处理器，冗余复数乘法器和可重构算术数据路径，以证明改善处理延迟，电路复杂性，门数和功耗的优势。并通过实验制作研究了多值集成电路工艺对器件性能的影响. [FDMA研究了基于频分多址（FDMA）和码分多址（CDMA）的集值逻辑结构。采用电流型CMOS工艺制作了一个基于ODMA的集值逻辑测试芯片，大大降低了布线复杂度。此外，通过控制M序列码的长度和复用度，可以灵活地控制芯片内数据传输中的误比特率。这一思想也被扩展到设计线高效的神经网络架构.【多波长光互连】提出了基于MCM的并行处理的多波长光互连网络，并开发了其关键器件“波长检测器”。结果表明，波长检测器可以区分8 - 16波长复用内的波导，这种程度的复用使得可能减少网络区域的复杂性的1/64 - 1/256的因素相比，一个单一的波长实现。[分子计算系统]研究了使用“酶晶体管”的分子计算架构。实验证实了酶晶体管的基本功能。

项目成果

M.Hiratsuka: "Enzyme transistor circuits for reaction-diffusion computing" IEEE Transactions on Circuits and Systems I : Fundamental Theory and Applications. 46. 294-303 (1999)

M.Hiratsuka：“用于反应扩散计算的酶晶体管电路”IEEE Transactions on Circuits and Systems I：基础理论和应用。

T.Higuchi and T.Aoki: "A multiplex computing paradigm" Methodologies for the Conception, Design, and application of Intelligent Systems (Proceedings of IIZUKA'96). Vol.1. 95-100 (1996)

T.Higuchi 和 T.Aoki：“多重计算范式”智能系统概念、设计和应用的方法（IIZUKA96 论文集）。

T.Aoki, H.Nogi, and T.Higuchi: "High-radix CORDIC algorithms for VLSI signal processing" Proc.of the 1997 IEEE Workshop on Signal Processing Systems. 183-192 (1997)

T.Aoki、H.Nogi 和 T.Higuchi：“用于 VLSI 信号处理的高基 CORDIC 算法”Proc.of 1997 IEEE 信号处理系统研讨会。

Y.Yuminaka, T.Aoki, and T.Higuchi: "Frequency-mode set-valued logic for wave-parallel computing -Design and experimental realization" Multiple- Valued Logic. Vol.3, No.4. 301-332 (1998)

Y.Yuminaka、T.Aoki 和 T.Higuchi：“波并行计算的频率模式集值逻辑 - 设计和实验实现”多值逻辑。

Y.Yuminaka: "Wave-parallel neural networks using orthogonal sequences" IEE Electronics Letters. 33. 690-691 (1997)

Y.Yuminaka：“使用正交序列的波并行神经网络”IEE 电子通讯。