BASIC STUDY ON HIGH-PERFORMANCE MULTIPLE-VALUED SUPER CHIP FOR INTELLIGENT ROBOTS

在传统的基于阵列结构的二进制算术电路中，运算速度受到进位传播的限制。在符号数字（SD）数系统中，进位传播总是被限制在左边的一个位置。然而，从集成电路实现的角度对SD数字系统进行了研究。本计画以实现由电流源、电流镜、阈值检测器及双向电流输入组成的多值双向电流模电路为开始。采用双向电流模电路，实现了SD全加法器。给出了用2位CMOS技术实现SD全加法器的电路布局。该模块由一个加法器、一个部分积生成器、一个商数字生成器、一个符号逆变器、两个编码器和四个布线块组成。利用得到的模块，通过适当指定模块之间的互连，可以实现基于加、减、乘、除的任何算术运算。这种模块化的实现对于半定制的VLSI门阵列是非常有用的。将所提出的SD乘法器与最快的二进制乘法器进行了比较。SD乘法器的时间与最快的二进制乘法器相当。然而，从降低设计复杂度的角度来看，SD乘法器要比二进制乘法器优越得多。最后，证明了多值技术的这些优点对智能机器人多值超级芯片的实现是有用的。对该芯片的性能进行了详细的评价。

In the conventional binary arithmetic circuits based on array structures, the operating speed is restricted by carry propagation. The carry propagation in the signed-digit (SD) number systems is always limited to one position to the left. However, the SD number systems have not been studied from the point of view of integrated circuit implementation.This project begins with implementation of the multiple-valued bidirectional current-mode circuits composed of current source, current mirrors, threshold detector, and bidirectional current input. Using the bidirectional currentmode circuits, the SD full adder is realized. The layout of the SD full adder is given with 2-mum CMOS technology. The module is constructed by an adder, a partial-product generator, a quotient digit generator, a sign invertor, two encoders and four wiring blocks.Using the modules thus obtained, any arithmetic operations based on addition, subtraction, multiplication and division can be realized by appropriately specifying the interconnection among the modules. This modular realization is very useful for semicustom VLSI as gate array. The comparison between the proposed SD multiplier and the fastest binary multiplier is carried out.The SD multiply time is comparable to that of the fastest binary multiplier. From the point of view of reduction in design complexity, however, the SD multiplier is much more superior to the binary multiplier.Lastly, it is demonstrated that these advantages of the multiple-valued technology are useful for implementation of the multiple-valued super chip for intelligent robots. The high-performance of the chip is also evaluated in detail.