A Study on Beyond-Binary Computing

当今的超大规模集成电路系统设计的基础上，二进制（基数-2）的算术算法结合二进制逻辑器件。随着超大规模集成电路（VLSI）技术向深亚微米几何尺寸发展，布线复杂性和延迟增加所导致的性能瓶颈变得越来越严重。本研究计画旨在探讨一种新的计算模式-超越二进位计算，以克服效能瓶颈的可能性。以下是本项目的主要成果：1.开发了使用非二进制冗余数系统的高速算术算法，并通过实验芯片制造证实了它们的性能。示例包括（i）基数-4并行除法器芯片，（ii）基数-2-4-8 CORDIC处理器芯片，（iii）使用SW算术的可配置数据路径芯片，以及（iv）使用冗余复数算术的真实的/复数可配置数据路径芯片。针对目标应用程序优化数字表示， ...更多信息 计算时间、功耗和布线复杂性的显著减少。通过现场可编程数字滤波器集成电路的设计，展示了多值逻辑集成电路技术与冗余算法相结合的影响。提出了设计超二进制电路和系统的新的CAD技术.设计并制作了一个以伪随机序列为信息载体的集值逻辑系统原型。该系统的基本原理被扩展到片内CDMA通信技术，这将有助于实现高度并行的计算架构，降低布线复杂度.开发了酶晶体管电路的计算机模拟和分析技术。这些技术被用来演示分子计算的一些应用，包括最优路径规划和图像处理。实验证实了使用人工催化剂器件（如酶晶体管）的无导线电路集成原理。少

The present-day VLSI systems are designed on the basis of binary (radix-2) arithmetic algorithms combined with binary logic devices. As the VLSI technology scales down to deep sub-micron geometry, performance bottlenecks caused by increased wiring complexity and delay are becoming significantly severe. This research project is to investigate a possibility of overcoming the performance bottlenecks by employing a new computing paradigm called "Beyond-Binary Computing". Listed below are major results of this project:1. High-speed arithmetic algorithms using non-binary redundant number systems were developed and their performances were confirmed through experimental chip fabrications. Examples include (i) a radix-4 parallel divider chip, (ii) a radix-2-4-8 CORDIC processor chip, (iii) a configurable datapath chip using SW arithmetic, and (iv) a real/complex reconfigurable datapath chip using redundant complex arithmetic. Optimizing number representation for target applications makes possib … More le drastic reduction in computation time, power consumption and wiring complexity. Impacts of multiple-valued logic IC technology combined with redundant arithmetic algorithms were demonstrated through the design of field-programmable digital filter ICs. Also, new CAD techniques for designing beyond-binary circuits and systems were proposed.2. A prototype of set-valued logic system, which uses pseudo-random sequences as information carriers, was designed and fabricated. The underlying principle of the fabricated system was extended to intra-chip CDMA communication techniques, which will be useful for implementing highly parallel computing architectures with reduced wiring complexity.3. Techniques for computer-based simulation and analysis for enzyme transistor circuits were developed. These techniques were used to demonstrate some applications of molecular computing, including optimal path planning and image processing. The principle of wire-free circuit integration using artificial catalyst devices, such as enzyme transistors, was confirmed experimentally. Less