IMPLEMENTATION OF ULTRA-HIGH-SPEED INFERENCE HARDWARE ENGINE BASED ON 4-VALUED CMOS INTEGRATED CIRCUITS AND ITS APPLICATION
基于四值CMOS集成电路的超高速推理硬件引擎的实现及其应用
基本信息
- 批准号:03555082
- 负责人:
- 金额:$ 2.24万
- 依托单位:
- 依托单位国家:日本
- 项目类别:Grant-in-Aid for Developmental Scientific Research (B)
- 财政年份:1991
- 资助国家:日本
- 起止时间:1991 至 1992
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
This project presents a dynamically rule-programmable, ultra-high-speed inference accelerator VLSI ( called hardware engine ) based on fully parallelpattern matching. Rules and attributes in the processor are essentially independent of one another, so that pattern matching operations can be performedin parallel by rules and attributes. Because each attribute is directly encoded by a single multiple-valued digit, one-digit pattern matching can beeasily described by only a 'programmable delta literal'. Moreover, a one-digit pattern matching cell can be simply implemented using a floating-gate MOSdevice, where threshold voltages correspond to the content of an attribute value. This property makes rule programming easily in such a pattern matchingcell.The layout of the proposed inference accelerator VLSI is given by using a 2 mum double-poly double-metal design rule. The effective size of the accelerator chip is about 7.0 x 8.0 ( mm^2 ) including 256 rules, 144 attributes and two types of … More conflict resolution circuit. Because each block in the VLSI processor is executed in parallel, ultra-high-speed inference can be achieved. Using SPICE2 simulation, the inference time is estimated at about 300 ns, which is about 1700 times faster than that of the conventional software-based systems with 32-bit 100 MIPS workstation.3-D objects are represented by graphs whose vertices and edges correspond to the apexes of objects and the line segments between apexes, respectively. In 3-D object recognition based on graph matching, one of the most important procedures is to find the best available sets ( called 'cliques') of mutually compatible assignments between two graphs, that is, 'clique finding'. As an application, a new highly parallel clique-finding VLSI processor for high-speed graph matching has been shown. The enhanced performance is attributed to the parallel search procedure operated in a digit pipelining and theuse of floating gate MOS devices. The proposed processor will be used in not only 3-D object recognition, but also several applications in fields that have structural data. Less
本计画提出一个基于全平行模式匹配的动态规则可程式化超高速推理加速器VLSI(称为硬体引擎)。处理器中的规则和属性本质上是相互独立的,因此模式匹配操作可以由规则和属性并行执行。因为每个属性都是直接用一个多值数字编码的,所以一位数模式匹配可以很容易地用一个“可编程增量文字”来描述。此外,一位数模式匹配单元可以简单地使用浮栅MOS器件来实现,其中阈值电压对应于属性值的内容。这种性质使得规则编程容易在这样的模式matchingcell。建议的推理加速器VLSI的布局给出了使用2妈妈双多晶硅双金属设计规则。加速器芯片的有效尺寸约为7.0 x 8.0(mm^2),包括256条规则,144个属性和两种类型的 ...更多信息 冲突解决电路因为VLSI处理器中的每个块是并行执行的,所以可以实现超高速推理。使用SPICE 2仿真,推理时间估计约为300 ns,这是约1700倍的速度比传统的基于软件的系统与32位100 MIPS工作站。3-D对象表示的图形,其顶点和边对应的顶点和顶点之间的线段,分别。在基于图匹配的三维物体识别中,最重要的步骤之一是寻找两个图之间相容的最佳分配集合(称为“团”),即“团发现”。作为一个应用,一个新的高度并行的查表查找VLSI处理器的高速图匹配已被证明。性能的提高是由于并行搜索过程中操作的数字流水线和浮栅MOS器件的使用。所提出的处理器将被用于不仅3-D对象识别,但也有几个应用领域的结构数据。少
项目成果
期刊论文数量(19)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
T.HANYU: "Dynamically Rule-Programmable VLSI Processor for Fully-Parallel Inference" Electronics Letters. 28. 695-697 (1992)
T.HANYU:“用于完全并行推理的动态规则可编程 VLSI 处理器”电子通讯。
- DOI:
- 发表时间:
- 期刊:
- 影响因子:0
- 作者:
- 通讯作者:
T. HANYU: "A MULTIPLE-VALUED LOGIC ARRAY VLSI BASED ON TWO-TRANSISTOR DELTA LITERAL CIRCUITS AND ITS APPLICATION TO REAL-TIME REASONING SYSTEM" PROC. 21ST IEEE INT. SYMP. ON MULTIPLE-VALUED LOGIC. 16-23 (1991)
T. Hanyu:“一种基于双晶体管Delta文字电路的多值逻辑阵列VLSI及其在实时推理系统中的应用”PROC。
- DOI:
- 发表时间:
- 期刊:
- 影响因子:0
- 作者:
- 通讯作者:
T. HANYU: "DIGIT-PIPELINED ON-CHIP CLIQUE-FINDING VLSI PROCESSOR FOR REAL-TIME 3-D OBJECT RECOGNITION" ELECTRONICS LETTERS. 28. 722-724 (1992)
T. Hanyu:“用于实时 3D 对象识别的数字管道片上团查找 VLSI 处理器”电子信件。
- DOI:
- 发表时间:
- 期刊:
- 影响因子:0
- 作者:
- 通讯作者:
T.Hanyu: "A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing" IEICE Trans.(電子情報通信学会英文誌). E74. 918-928 (1991)
T. Hanyu:“用于关联处理的高密度多级匹配阵列芯片的设计”IEICE Trans(电子、信息和通信工程师学会英文期刊)918-928(1991)。
- DOI:
- 发表时间:
- 期刊:
- 影响因子:0
- 作者:
- 通讯作者:
T.Hanyu: "A Multiple-Valued Logic Array VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning System" Proc.21st IEEE Int.Symp.on Multiple-Valued Logic. 16-23 (1991)
T.Hanyu:“基于双晶体管 Delta 文字电路的多值逻辑阵列 VLSI 及其在实时推理系统中的应用”Proc.21st IEEE Int.Symp.on 多值逻辑。
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- 影响因子:0
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HIGUCHI Tatsuo其他文献
HIGUCHI Tatsuo的其他文献
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{{ truncateString('HIGUCHI Tatsuo', 18)}}的其他基金
System Integration of Beyond-Binary Computing
超越二进制计算的系统集成
- 批准号:
17300022 - 财政年份:2005
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
New Developments for Beyond-Binary Computing
超越二进制计算的新发展
- 批准号:
14380130 - 财政年份:2002
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of Configurable Signal Processors Using Redundant Arithmetic Algorithms
使用冗余算术算法开发可配置信号处理器
- 批准号:
11558028 - 财政年份:1999
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
A Study on Beyond-Binary Computing
超越二进制计算的研究
- 批准号:
11480058 - 财政年份:1999
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of an Integrated Multiwavelength Optical Computing System
集成多波长光学计算系统的开发
- 批准号:
08558022 - 财政年份:1996
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for Scientific Research (A)
A Study of Highly Parallel Computing Based on Set-Valued Logic
基于集值逻辑的高度并行计算研究
- 批准号:
08458058 - 财政年份:1996
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of Highly Parallel Optical Multiplex Computing Systems
高度并行光复用计算系统的开发
- 批准号:
05558025 - 财政年份:1993
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
Multidimensional digital signal processing systems for the next generation visual communication
用于下一代视觉通信的多维数字信号处理系统
- 批准号:
05452201 - 财政年份:1993
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for General Scientific Research (B)
BASIC STUDY ON HIGH-PERFORMANCE MULTIPLE-VALUED SUPER CHIP FOR INTELLIGENT ROBOTS
智能机器人高性能多值超级芯片基础研究
- 批准号:
01460157 - 财政年份:1989
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for General Scientific Research (B)
SYSTEMATIC STUDY ON THEORY AND TECHNOLOGY OF HIGHLY PARALLEL DIGITAL SIGNAL PROCESSING
高度并行数字信号处理理论与技术系统研究
- 批准号:
63302035 - 财政年份:1988
- 资助金额:
$ 2.24万 - 项目类别:
Grant-in-Aid for Co-operative Research (A)