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System Integration of Beyond-Binary Computing

超越二进制计算的系统集成

基本信息

批准号：
17300022
负责人：
HIGUCHI Tatsuo
金额：
$ 4.89万
依托单位：
Tohoku Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2005
资助国家：
日本
起止时间：
2005 至 2007
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-17300022/
关键词：
Computer System System on Chip Micro-nano- devices Multiple-Valued Logic Electric Desien Automation

项目摘要

The present-day VLSI systems are designed on the basis of binary (radix-2) arithmetic algorithms combined with binary logic devices. As the VLSI technology scales down to deep sub-micron geometry, performance bottlenecks caused by increased wiring complexity and delay are becoming significantly severe. In order to overcome the performance bottlenecks, this research project investigates system integration based on a novel computing paradigm called "Beyond-Binary Computing". Listed below are major results of this project :1. A hardware description language called ARITH was developed for describing hardware algorithms in VLSI systems. By using ARUM, we developed an advanced library containing high-performance arithmetic algorithms using both binary and non-binary number systems. As an application, we used the proposed library to develop a practical module generator supporting various multiplier structures. The generator is available from our website, and is widely used all over the world. … More 2. A new high-level design method with ARITH was developed for designing high-performance beyond-binary arithmetic circuits. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. For the prototype design, we used voltage-mode and current-mode CMOS technologies for binary logic and multiple-valued logic, respectively. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelf place-and-route tool. The capability of the proposed method was investigated through some arithmetic circuit designs.3. A content-addressable memory circuits based on Single-Electron Transistors (SETs) was developed and evaluated for studying next-generation low-power LSI circuits. Also, a redox microarray for wire-free circuit integration using artificial catalyst devices was investigated experimentally. A prototype of redox microarray was demonstrated through an excitable reaction-diffusion dynamics, which was implemented by chemical reaction(e.g. B-Z reaction)waves. The visualization of the chemical waves was also investigated. Less

当今的超大规模集成电路系统设计的基础上，二进制（基数-2）的算术算法结合二进制逻辑器件。随着超大规模集成电路（VLSI）技术向深亚微米几何尺寸发展，布线复杂性和延迟增加所导致的性能瓶颈变得越来越严重。为了克服性能瓶颈，本研究计划研究基于一种称为“超越二进制计算”的新计算范式的系统集成。以下是本项目的主要成果：1.硬件描述语言ARITH是为描述VLSI系统中的硬件算法而开发的。通过使用ARUM，我们开发了一个包含使用二进制和非二进制数字系统的高性能算术算法的高级库。作为一个应用，我们使用建议库开发一个实用的模块生成器，支持各种乘法器结构。该发电机可从我们的网站上获得，并在世界各地广泛使用。 ...更多信息 2.针对高性能超二进制运算电路的设计，提出了一种新的ARITH高级设计方法。ARITH描述可以转化为二进制/多值融合逻辑中的技术依赖的网表。对于原型设计，我们使用电压模式和电流模式的CMOS技术的二进制逻辑和多值逻辑，分别。将网表转换为物理布局图案的过程由现成的布局布线工具自动执行。通过设计运算电路验证了该方法的性能.为研究下一代低功耗大规模集成电路，提出了一种基于单电子晶体管（SET）的内容寻址存储器电路。此外，氧化还原微阵列的无导线电路集成使用人工催化剂设备进行了实验研究。氧化还原微阵列的原型是通过一个可激发的反应扩散动力学，这是由化学反应（如B-Z反应）波实现的。化学波的可视化也进行了研究。少

项目成果

期刊论文数量（0）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multinle-Valued Current-Mode Logic

使用多值电流模式逻辑现场可编程数字滤波器 LSI 的原型制造

DOI：
发表时间：
2005
期刊：
Journal of Multiple-Valued Logic and Soft Computing 11
影响因子：
0
作者：
N. Homma;Y. Watanabe;T. Aoki;T. Higuchi;Yuki Watanabe;Naofumi Homma;Katsuhiko Degawa;Koichi Ito;Naofumi Homma;Naofumi Homma;Koichi Ito;Yuki Watanabe;Sei Nagashima;Koichi Ito;Hiroshi Nakajima;中島寛;Koichi Ito;Katsuhiko Degawa;Yoshifumi Sasaki;Masanori Natsui;Katsuhiko Degawa
通讯作者：
Katsuhiko Degawa

Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects

使用多值电流模式逻辑的现场可编程数字滤波器 LSI 的原型制造 - 器件扩展和未来前景