SYSTEMATIC STUDY ON THEORY AND TECHNOLOGY OF HIGHLY PARALLEL DIGITAL SIGNAL PROCESSING

在大多数实时数字信号处理应用中，通用并行计算机不能提供令人满意的处理速度。特别地，在二维（2-D）或三维（3-D）信号应用中对速度和性能的日益增长的需求需要革命性的计算技术。本课题从二维、三维数字滤波器和离散傅立叶变换的基本理论入手，系统地研究了实时高并行数字信号处理的理论与技术，包括高并行信号处理的基本理论、硬件算法和体系结构设计。为了发展多维数字信号处理，不仅需要硬件的发展，而且需要寻求有效的设计技术。提出了一种基于降维分解设计的二维和三维可分离分母数字滤波器的设计方法。在实时信号处理中，加法器和乘法器的高速实现是最重要的。本课题提出了一种新的基于符号数字（SD）的硬件算法。在SD数表示中，加法和减法期间的猫传播总是限于左侧的一个位置。数制的这个性质不仅对加法非常有用，而且对乘法也非常有用。在实际应用中，加法器和乘法器采用乘法电流模电路设计，并采用CMOS工艺实现。它被证实，这里得到的加法器和乘法器上级最快的二进制的速度。最后，研究并设计了二维和三维数字滤波器的高度并行处理结构。提出的架构的董事会实施进行。该系统已成功地应用于二维和三维信号的实时应用。

In most real-time digital signal processing application, general-Purpose parallel computers cannot offer satisfactory processing speed. Particularly, the increasing demands of speed and performance in two-dimensional (2-D) or three-dimensional (3-D) signal applications necessitate a revolutional computing technology. This project is to study systematically on theory and technology of highly parallel digital signal processing in real-time, which includes the following contents : basic theory, hardware algorithms, and architecture design for highly parallel signal processing.The project begins with basic theory of 2-D and 3-D digital filters and discrete Fourier transform. In order to develop multidimensional digital signal processing, it is needed not only to develop hardware, but also to search efficient design techniques. The investigators propose a design technique of 2-D and 3-D separable denominator digital filters based on the reduced-dimensional decomposition design. Thus computational effort needed in the design procedure can be reduced.In real-time signal processing, realization of high speed in adder and multiplier is most important. This project gives a new hardware algorithm based on the signed-digit (SD) number. In the SD number representation, catry propagation during addition and subtraction is always limited to one position to the left. This property of the number system is very useful not only for addition but also for multiplication. Practically, adder and multiplier are designed using multiplevalued current-mode circuit and implemented in CMOS technology. It is confirmed that the adder and multiplier obtained here are superior to the fastest binary ones in term of speed. Finally, highly parallel processing architecture is studied and designed in 2-D and 3-D digital filters. Board implementation of proposed architecture is carried out. The system is successfully applied to real-time application of 2-D and 3-D signals.