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SYSTEMATIC STUDY ON THEORY AND TECHNOLOGY OF HIGHLY PARALLEL DIGITAL SIGNAL PROCESSING

高度并行数字信号处理理论与技术系统研究

基本信息

批准号：
63302035
负责人：
HIGUCHI Tatsuo
金额：
$ 2.82万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Co-operative Research (A)
财政年份：
1988
资助国家：
日本
起止时间：
1988 至 1989
项目状态：
已结题

项目摘要

In most real-time digital signal processing application, general-Purpose parallel computers cannot offer satisfactory processing speed. Particularly, the increasing demands of speed and performance in two-dimensional (2-D) or three-dimensional (3-D) signal applications necessitate a revolutional computing technology. This project is to study systematically on theory and technology of highly parallel digital signal processing in real-time, which includes the following contents : basic theory, hardware algorithms, and architecture design for highly parallel signal processing.The project begins with basic theory of 2-D and 3-D digital filters and discrete Fourier transform. In order to develop multidimensional digital signal processing, it is needed not only to develop hardware, but also to search efficient design techniques. The investigators propose a design technique of 2-D and 3-D separable denominator digital filters based on the reduced-dimensional decomposition design. Thus computational effort needed in the design procedure can be reduced.In real-time signal processing, realization of high speed in adder and multiplier is most important. This project gives a new hardware algorithm based on the signed-digit (SD) number. In the SD number representation, catry propagation during addition and subtraction is always limited to one position to the left. This property of the number system is very useful not only for addition but also for multiplication. Practically, adder and multiplier are designed using multiplevalued current-mode circuit and implemented in CMOS technology. It is confirmed that the adder and multiplier obtained here are superior to the fastest binary ones in term of speed. Finally, highly parallel processing architecture is studied and designed in 2-D and 3-D digital filters. Board implementation of proposed architecture is carried out. The system is successfully applied to real-time application of 2-D and 3-D signals.

在大多数实时数字信号处理应用中，通用并行计算机不能提供令人满意的处理速度。特别是，二维(2-D)或三维(3-D)信号应用中对速度和性能的日益增长的需求需要一种革命性的计算技术。本课题对高并行实时数字信号处理的理论和技术进行了系统的研究，主要内容包括：高并行信号处理的基础理论、硬件算法和体系结构设计。为了发展多维数字信号处理，不仅需要开发硬件，还需要寻找有效的设计技术。研究人员提出了一种基于降维分解设计的二维和三维可分离分母数字滤波器的设计方法。在实时信号处理中，加法器和乘法器的高速实现是重中之重。本课题提出了一种新的基于符号位(SD)数的硬件算法。在SD数表示中，加法和减法过程中的Catry传播总是被限制在左侧的一个位置。数制的这一性质不仅对加法很有用，而且对乘法也很有用。实际上，加法器和乘法器都是用多值电流模式电路设计的，并用CMOS工艺实现。结果表明，该加法器和乘法器在速度上优于最快的二进制加法器和乘法器。最后，对二维和三维数字滤波器的高度并行处理结构进行了研究和设计。对所提出的体系结构进行了板级实现。该系统已成功应用于2-D和3-D信号的实时应用。