Study on extremely thin barriers in low-resistivity against Cu interconnect on field oxide layer of SiO_2

在未来的超大规模集成电路系统互连技术中，为了减少系统中RC信号的延迟，需要65 nm规则可接受的低电阻率的极薄势垒。在Cu/barrier/SiO_2/Si模型系统中，我们从（1）低阻势垒、（2）Cu[111]择优取向势垒和（3）极薄势垒的角度研究了可能的势垒材料。我们提出了使用Ta-W合金来避免Ta中的高电阻的四方晶系多晶相，并确认了形成Cu[111]织构的低电阻势垒。由这一结果可以看出，体心立方金属Nb是Cu[111]织构形成的阻挡层，并证实了Cu[111]/Nb[110]/SiO_2/Si系统的成功形成。我们还在SiO_2上用纳米晶VN薄膜对Cu形成了厚度为10 nm的阻挡层。在600℃退火1h后，薄膜的阻挡层没有Cu的扩散，具有良好的阻挡性能。此外，还提出了厚度为1.5nm的VN势垒的高性能。

In the interconnecting technology for system-ULSI's in future, extremely thin barriers in low-resistivity acceptable to the 65nm rule were desired for reducing the RC signal delay in the system. We examined the possible barrier materials from the points of view of (1) low-resistive barrier, (2) barrier for Cu[111] preferred orientation and (3) extremely thin barrier in the model system of Cu/barrier/SiO_2/Si. We proposed the use of Ta-W alloy to avoid the high-resistive tetragonal polymorphic phase in Ta, and confirmed the low-resistive barrier on which Cu[111] texture was formed. From this result, Nb as a bcc metal was examined as the barrier on which Cu[111] texture was obtained, and the successful formation of preferentially oriented Cu[111]/Nb[110]/SiO_2/Si system was confirmed. We also applied a nano-crystalline VN film to a barrier as thin as 〜10nm against Cu on SiO_2. The excellent barrier performance without any diffusion of Cu through the thin VN barrier due to annealing at 600℃ for 1h was obtained. Furthermore, the high performance of 〜5nm thick VN barrier was also suggested.