Study on extremely thin barriers in low-resistivity against Cu interconnect on field oxide layer of SiO_2

在未来的系统- ulsi互连技术中，需要在65nm规则下可接受的低电阻率的极薄屏障，以减少系统中的RC信号延迟。我们从(1)低阻势垒，(2)Cu[111]择优取向势垒，(3)Cu/势垒/SiO_2/Si模型体系中极薄势垒的角度考察了可能的势垒材料。我们提出使用Ta- w合金来避免Ta中的高电阻四方多晶相，并确认了Cu[111]织构形成的低电阻势垒。在此基础上，对Cu[111]织构的形成进行了研究，确定了Cu[111]/Nb[110]/SiO_2/Si优先取向体系的成功形成。我们还在SiO_2上制备了厚度约为10nm的纳米晶体VN膜来阻挡Cu。在600℃下退火1h，获得了优异的势垒性能，没有Cu在VN薄势垒中扩散。此外，还提出了~ 5nm厚VN势垒的高性能。

In the interconnecting technology for system-ULSI's in future, extremely thin barriers in low-resistivity acceptable to the 65nm rule were desired for reducing the RC signal delay in the system. We examined the possible barrier materials from the points of view of (1) low-resistive barrier, (2) barrier for Cu[111] preferred orientation and (3) extremely thin barrier in the model system of Cu/barrier/SiO_2/Si. We proposed the use of Ta-W alloy to avoid the high-resistive tetragonal polymorphic phase in Ta, and confirmed the low-resistive barrier on which Cu[111] texture was formed. From this result, Nb as a bcc metal was examined as the barrier on which Cu[111] texture was obtained, and the successful formation of preferentially oriented Cu[111]/Nb[110]/SiO_2/Si system was confirmed. We also applied a nano-crystalline VN film to a barrier as thin as 〜10nm against Cu on SiO_2. The excellent barrier performance without any diffusion of Cu through the thin VN barrier due to annealing at 600℃ for 1h was obtained. Furthermore, the high performance of 〜5nm thick VN barrier was also suggested.