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Improving Crystal Conditions of Compound Semiconductors Laterally Grown on Metal Wire

改善金属线上横向生长的化合物半导体的晶体条件

基本信息

批准号：
11450006
负责人：
MIYAMOTO Yasuyuki
金额：
$ 8.83万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1999
资助国家：
日本
起止时间：
1999 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-11450006/
关键词：
Tungsten Wire Electron Wave Biprism Coherent Emitter Lateral Coherence OMVPE Embedding Tungsten Attractive Potential Double Barrier Resonant Emitter

项目摘要

Fabrication of Tungsten Wire with Low Resistance and High Aspect RatioTo improve electrical performance of Tungsten wire, a Tungsten film with a conductivity of about six times higher than that in bulk has been achieved by sputtering evaporation. A wire width of 100 nm and an aspect ratio of about 1 have been also achieved by a combination of the electron beam exposure and the reactive ion etching (RIE).Crystal Growth to Bury Tungsten Wire by MOVPE and Its Crystalline Estimation by HBTDependences of lateral growth of GaAs and InP to bury Tungsten wire on gas sources and growth conditions have been revealed. Crystal conditions close to buried metal surface have been also revealed to be acceptable since sufficient current gains of heterojunction bipolar transistors fabricated on the buried metal have been obtained. Moreover, electric conditions close at the interface between InP and buried metal wire has been estimated by means of high-frequency characteristics of sub-micron size transis … More tor. As a result, the electric conditions close at the interface have depended on temperature at crystal growth to bury Tungsten wire. It is reasonable to consider there have been generated carriers from impurities diffusing from Tungsten wire and the carrier density can be considered to be reduced by improving a purity of Tungsten wire and lowering a temperature at crystal growth to bury Tungsten wire.Fabrication of a Novel Transistor with a Metal Wire GateWe have fabricated a novel transistor where hot electrons are generated and travel through undoped semiconductor region by adopting a combination of double-barrier resonant-tunneling structure and buried metal gate. A reduction of emitter-gate leakage current has been achieved by using a semi-insulating substrate and wiring the buried metal and contact pad through a free-standing wire realized by etching semiconductor. From measured I-V characteristics, it has been confirmed there has been realized attractive potential around the buried metallic gate and we have been able to show the potential of our device. Less

低电阻高长径比钨丝的制备为了提高钨丝的电性能，采用溅射蒸发的方法制备了导电率比体相高6倍的钨薄膜。通过电子束曝光和反应离子刻蚀（RIE）的结合，也获得了100 nm的线宽和约1的纵横比。埋钨丝的MOVPE晶体生长和HBT晶体评价揭示了埋钨丝的GaAs和InP横向生长对气源和生长条件的依赖性。由于在埋层金属上制造的异质结双极晶体管获得了足够的电流增益，因此接近埋层金属表面的晶体条件也是可以接受的。此外，还利用亚微米尺寸的晶体管的高频特性估算了InP与埋层金属丝界面附近的电性条件 ...更多信息 tor。因此，界面附近的电条件依赖于晶体生长时的温度来掩埋钨丝。可以合理地认为，从钨丝扩散的杂质已经产生了载流子，并且可以认为通过提高钨丝的纯度和降低晶体生长时的温度以掩埋钨丝来降低载流子密度。双势垒共振隧穿结构和掩埋金属栅的组合。通过半绝缘衬底和通过蚀刻半导体实现的独立布线来布线掩埋金属和接触焊盘，已经实现了发射极-栅极漏电流的减小。从测量的I-V特性，它已被证实有已实现的周围的掩埋金属栅极的吸引力的潜力，我们已经能够显示我们的设备的潜力。少