Improving Crystal Conditions of Compound Semiconductors Laterally Grown on Metal Wire

低电阻、高纵横比钨丝的制备为了提高钨丝的电性能，采用溅射蒸发的方法制备了导电率比普通钨丝高6倍的钨丝薄膜。通过电子束曝光和反应离子刻蚀（RIE）相结合，还获得了100 nm的线宽和约1的长宽比。揭示了GaAs和InP在埋钨丝中横向生长对气源和生长条件的依赖性。由于在埋藏金属上制造的异质结双极晶体管获得了足够的电流增益，因此接近埋藏金属表面的晶体条件也是可以接受的。此外，利用亚微米尺寸过渡的高频特性，估计了InP与埋地金属线交界面的电气条件。结果表明，靠近界面的电条件取决于晶体生长时的温度来埋藏钨丝。可以认为杂质从钨丝中扩散产生了载流子，可以认为通过提高钨丝纯度和降低晶体生长温度来埋藏钨丝，从而降低载流子密度。采用双势垒谐振隧穿结构和埋地金属栅极相结合的方法，制备了一种产生热电子并通过未掺杂半导体区域的新型晶体管。通过使用半绝缘衬底并通过蚀刻半导体实现的独立导线将埋藏的金属和接触垫连接起来，可以减少发射栅泄漏电流。从测量的I-V特性，已经证实在埋藏的金属栅极周围已经实现了吸引电位，我们已经能够展示我们的设备的潜力。少

Fabrication of Tungsten Wire with Low Resistance and High Aspect RatioTo improve electrical performance of Tungsten wire, a Tungsten film with a conductivity of about six times higher than that in bulk has been achieved by sputtering evaporation. A wire width of 100 nm and an aspect ratio of about 1 have been also achieved by a combination of the electron beam exposure and the reactive ion etching (RIE).Crystal Growth to Bury Tungsten Wire by MOVPE and Its Crystalline Estimation by HBTDependences of lateral growth of GaAs and InP to bury Tungsten wire on gas sources and growth conditions have been revealed. Crystal conditions close to buried metal surface have been also revealed to be acceptable since sufficient current gains of heterojunction bipolar transistors fabricated on the buried metal have been obtained. Moreover, electric conditions close at the interface between InP and buried metal wire has been estimated by means of high-frequency characteristics of sub-micron size transis … More tor. As a result, the electric conditions close at the interface have depended on temperature at crystal growth to bury Tungsten wire. It is reasonable to consider there have been generated carriers from impurities diffusing from Tungsten wire and the carrier density can be considered to be reduced by improving a purity of Tungsten wire and lowering a temperature at crystal growth to bury Tungsten wire.Fabrication of a Novel Transistor with a Metal Wire GateWe have fabricated a novel transistor where hot electrons are generated and travel through undoped semiconductor region by adopting a combination of double-barrier resonant-tunneling structure and buried metal gate. A reduction of emitter-gate leakage current has been achieved by using a semi-insulating substrate and wiring the buried metal and contact pad through a free-standing wire realized by etching semiconductor. From measured I-V characteristics, it has been confirmed there has been realized attractive potential around the buried metallic gate and we have been able to show the potential of our device. Less