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Improving Crystal Conditions of Compound Semiconductors Laterally Grown on Metal Wire

改善金属线上横向生长的化合物半导体的晶体条件

基本信息

批准号：
11450006
负责人：
MIYAMOTO Yasuyuki
金额：
$ 8.83万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1999
资助国家：
日本
起止时间：
1999 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-11450006/
关键词：
Tungsten Wire Electron Wave Biprism Coherent Emitter Lateral Coherence OMVPE Embedding Tungsten Attractive Potential Double Barrier Resonant Emitter

项目摘要

Fabrication of Tungsten Wire with Low Resistance and High Aspect RatioTo improve electrical performance of Tungsten wire, a Tungsten film with a conductivity of about six times higher than that in bulk has been achieved by sputtering evaporation. A wire width of 100 nm and an aspect ratio of about 1 have been also achieved by a combination of the electron beam exposure and the reactive ion etching (RIE).Crystal Growth to Bury Tungsten Wire by MOVPE and Its Crystalline Estimation by HBTDependences of lateral growth of GaAs and InP to bury Tungsten wire on gas sources and growth conditions have been revealed. Crystal conditions close to buried metal surface have been also revealed to be acceptable since sufficient current gains of heterojunction bipolar transistors fabricated on the buried metal have been obtained. Moreover, electric conditions close at the interface between InP and buried metal wire has been estimated by means of high-frequency characteristics of sub-micron size transis … More tor. As a result, the electric conditions close at the interface have depended on temperature at crystal growth to bury Tungsten wire. It is reasonable to consider there have been generated carriers from impurities diffusing from Tungsten wire and the carrier density can be considered to be reduced by improving a purity of Tungsten wire and lowering a temperature at crystal growth to bury Tungsten wire.Fabrication of a Novel Transistor with a Metal Wire GateWe have fabricated a novel transistor where hot electrons are generated and travel through undoped semiconductor region by adopting a combination of double-barrier resonant-tunneling structure and buried metal gate. A reduction of emitter-gate leakage current has been achieved by using a semi-insulating substrate and wiring the buried metal and contact pad through a free-standing wire realized by etching semiconductor. From measured I-V characteristics, it has been confirmed there has been realized attractive potential around the buried metallic gate and we have been able to show the potential of our device. Less

低电阻、高纵横比钨丝的制造为了提高钨丝的电性能，通过溅射蒸发获得了电导率比块体高约六倍的钨薄膜。通过电子束曝光和反应离子蚀刻 (RIE) 的组合，还实现了 100 nm 的线宽和约 1 的深宽比。通过 MOVPE 埋入钨线的晶体生长及其通过 HBT 的晶体估计揭示了埋入钨线的 GaAs 和 InP 横向生长对气体源和生长条件的依赖性。由于在埋入金属上制造的异质结双极晶体管已经获得了足够的电流增益，因此接近埋入金属表面的晶体条件也已被证明是可接受的。此外，通过亚微米尺寸晶体管的高频特性，可以估计 InP 和埋入金属线之间界面附近的电气条件。因此，界面附近的电条件取决于埋藏钨丝的晶体生长时的温度。可以合理地认为，从钨丝中扩散的杂质产生了载流子，并且可以认为通过提高钨丝的纯度和降低晶体生长温度以掩埋钨丝来降低载流子密度。带有金属线栅的新型晶体管的制造我们已经制造了一种新型晶体管，其中产生热电子并通过采用组合方式穿过未掺杂的半导体区域双势垒谐振隧道结构和埋入金属栅极。通过使用半绝缘基板并通过蚀刻半导体实现的独立导线对埋入金属和接触焊盘进行布线，可以减少发射极-栅极漏电流。从测量的 I-V 特性来看，已经证实埋入金属栅极周围已经实现了有吸引力的潜力，并且我们已经能够展示我们的器件的潜力。较少的