Improving Crystal Conditions of Compound Semiconductors Laterally Grown on Metal Wire

改善金属线上横向生长的化合物半导体的晶体条件

基本信息

批准号：
11450006
负责人：
MIYAMOTO Yasuyuki
金额：
$ 8.83万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1999
资助国家：
日本
起止时间：
1999 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-11450006/
关键词：
Tungsten Wire Electron Wave Biprism Coherent Emitter Lateral Coherence OMVPE Embedding Tungsten Attractive Potential Double Barrier Resonant Emitter

项目摘要

Fabrication of Tungsten Wire with Low Resistance and High Aspect RatioTo improve electrical performance of Tungsten wire, a Tungsten film with a conductivity of about six times higher than that in bulk has been achieved by sputtering evaporation. A wire width of 100 nm and an aspect ratio of about 1 have been also achieved by a combination of the electron beam exposure and the reactive ion etching (RIE).Crystal Growth to Bury Tungsten Wire by MOVPE and Its Crystalline Estimation by HBTDependences of lateral growth of GaAs and InP to bury Tungsten wire on gas sources and growth conditions have been revealed. Crystal conditions close to buried metal surface have been also revealed to be acceptable since sufficient current gains of heterojunction bipolar transistors fabricated on the buried metal have been obtained. Moreover, electric conditions close at the interface between InP and buried metal wire has been estimated by means of high-frequency characteristics of sub-micron size transis … More tor. As a result, the electric conditions close at the interface have depended on temperature at crystal growth to bury Tungsten wire. It is reasonable to consider there have been generated carriers from impurities diffusing from Tungsten wire and the carrier density can be considered to be reduced by improving a purity of Tungsten wire and lowering a temperature at crystal growth to bury Tungsten wire.Fabrication of a Novel Transistor with a Metal Wire GateWe have fabricated a novel transistor where hot electrons are generated and travel through undoped semiconductor region by adopting a combination of double-barrier resonant-tunneling structure and buried metal gate. A reduction of emitter-gate leakage current has been achieved by using a semi-insulating substrate and wiring the buried metal and contact pad through a free-standing wire realized by etching semiconductor. From measured I-V characteristics, it has been confirmed there has been realized attractive potential around the buried metallic gate and we have been able to show the potential of our device. Less

具有低阻力和高方面的钨丝的制造，改善了钨丝的电性能，钨丝电线的电能型膜的电导率比散布经济的电导率高约六倍。 A wire width of 100 nm and an aspect ratio of about 1 have also been achieved by a combination of the electron beam exposure and the reactive ion etching (RIE).Crystal Growth to Bury Tungsten Wire by MOVPE and Its Crystalline Estimation by HBTDependences of lateral growth of GaAs and InP to bury Tungsten wire on gas sources and growth conditions have been revealed.由于已经获得了在埋入金属上制造的杂晶双极晶体管的足够电流增长，因此还揭示了接近埋入金属表面的晶体条件。此外，通过INP和埋藏金属丝之间接近的电气状况通过亚微米尺寸transis的高频特性估算了估计。结果，界面上关闭的电气条件取决于晶体生长时的温度，以掩埋钨丝。有理由认为，已经从钨丝传播的杂质中产生了载体，并且可以认为载体密度可以通过提高钨丝的纯度并在晶体生长时降低温度来降低载体密度，从而掩埋了钨丝的温度，从而掩埋了用新颖的跨性能的跨晶体管来掩埋，并通过新颖的跨性能来制造新颖的跨性别，并通过新颖的转移者产生了一定的电子产品，并且是由新颖的转移者生成的。双屏障谐振结构和建造金属门的组合。通过使用半胰上的基板并通过蚀刻半导体实现的独立电线将内置的金属和接触垫接线，可以减少发射线闸门泄漏电流。从测得的I-V特性中，已经证实已经在建筑金属栅极周围实现了有吸引力的潜力，我们已经能够展示设备的潜力。较少的