Improving Crystal Conditions of Compound Semiconductors Laterally Grown on Metal Wire

为提高钨丝的电学性能，采用溅射蒸发法制备了一种电导率约为块体的6倍的钨膜。通过电子束曝光和反应离子刻蚀(RIE)相结合的方法，也获得了100 nm的线宽和约1的长径比。用MOVPE方法生长钨线材，并用HBT估算其结晶度，揭示了GaAs和InP横向生长埋钨线材对气源和生长条件的依赖。接近埋入金属表面的结晶条件也是可以接受的，因为在埋入金属上制作的异质结双极晶体管获得了足够的电流增益。此外，还利用亚微米级…的高频特性估计了InP与埋地金属线界面附近的电学条件更多的是。结果表明，接近界面处的电条件依赖于晶体生长时的温度来掩埋钨丝。通过提高钨丝的纯度和降低晶体生长时的温度来掩埋钨丝，可以认为可以降低载流子密度。制作一种新型的金属线栅晶体管我们采用双势垒共振隧穿结构和埋入金属栅相结合的方法制作了一种新型的晶体管，它可以产生热电子并通过未掺杂的半导体区传输。通过使用半绝缘衬底，通过腐蚀半导体实现的自由导线将埋入金属和触点焊盘布线，从而实现了发射极栅漏电流的降低。从测量的I-V特性来看，已经证实在埋入的金属栅周围已经实现了吸引人的电势，并且我们已经能够显示出我们的器件的潜力。较少

Fabrication of Tungsten Wire with Low Resistance and High Aspect RatioTo improve electrical performance of Tungsten wire, a Tungsten film with a conductivity of about six times higher than that in bulk has been achieved by sputtering evaporation. A wire width of 100 nm and an aspect ratio of about 1 have been also achieved by a combination of the electron beam exposure and the reactive ion etching (RIE).Crystal Growth to Bury Tungsten Wire by MOVPE and Its Crystalline Estimation by HBTDependences of lateral growth of GaAs and InP to bury Tungsten wire on gas sources and growth conditions have been revealed. Crystal conditions close to buried metal surface have been also revealed to be acceptable since sufficient current gains of heterojunction bipolar transistors fabricated on the buried metal have been obtained. Moreover, electric conditions close at the interface between InP and buried metal wire has been estimated by means of high-frequency characteristics of sub-micron size transis … More tor. As a result, the electric conditions close at the interface have depended on temperature at crystal growth to bury Tungsten wire. It is reasonable to consider there have been generated carriers from impurities diffusing from Tungsten wire and the carrier density can be considered to be reduced by improving a purity of Tungsten wire and lowering a temperature at crystal growth to bury Tungsten wire.Fabrication of a Novel Transistor with a Metal Wire GateWe have fabricated a novel transistor where hot electrons are generated and travel through undoped semiconductor region by adopting a combination of double-barrier resonant-tunneling structure and buried metal gate. A reduction of emitter-gate leakage current has been achieved by using a semi-insulating substrate and wiring the buried metal and contact pad through a free-standing wire realized by etching semiconductor. From measured I-V characteristics, it has been confirmed there has been realized attractive potential around the buried metallic gate and we have been able to show the potential of our device. Less