Ultrafine/High-speed electron devices based on buried nano-metal-wires in compound semiconductors
Ultrafine/High-speed electron devices based on buried nano-metal-wires in compound semiconductors
批准号:
14350182
负责人:
MIYAMOTO Yasuyuki
金额:
$9.66万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
2002
资助国家:
日本
项目状态:
已结题
起止时间:
2002 至 2003
中文摘要
本论文的研究工作主要包括以下两个方面:1.埋层纳米金属线作为栅极的电子引出结构我们制作了埋层纳米金属线作为栅极的电子引出结构的热电子晶体管,在直流特性方面,证实了饱和的I-V特性,为了抑制从发射极到栅极的电流注入,发明了新的结构(已申请专利),并且发射极电流与栅极电流之间的比率提高到几十。从测试的直流特性估算出InP本征值为10 mS,为了减少电子的散射,确定了InP本征层的纯度。结果,在AlInAs/InP HEMT结构中确认了77 K下的110,000 cm ^2/Vs的电子迁移率。当去除Si掺杂层时,确认了77 K下的220,000 cm ^2/Vs的电子迁移率。据我们所知,77 K的流动性是世界纪录。2.埋层纳米金属线集电体结构通过晶体生长研究,发现金属线上覆盖层的厚度随金属线的数目而变化。由于晶体生长的失败是由于这种现象,我们制造的结构,只有一个线作为集电极与细化的晶体生长条件。因此,我们制作了一个纳米金属线作为收集极的HBT。该器件的发射极面积为0.1μm×0.5μm。据我们所知,这个面积是最小的异质结双极晶体管。作为接触电阻,通过改变电极材料(从钛到钯),发射极接触电阻率从3 × 10 <-6>^Wcm ^2降低到1 × 10 ^<-6>Wcm ^2,基极接触电阻率从2.5 × 10 <-6>^Wcm ^2降低到3 × 10 ^<-7>Wcm ^2。这种减小与小的集电极电容相结合对于获得良好的微波性能是非常重要的。
英文摘要
Our researches consisted of following two terms.1.Emitter structure for extraction of electrons by buried nano-metal-wires as gateWe fabricated hot electron transistors with buried nano-metal -wires to extract ion of electron. In DC characteristics, saturated I-V characteristics was confirmed.To suppress current injection from emitter to gate, new structure was invented (patent applied for) and ratio between emitter current vs. gate current was enhanced to several tens. Estimated transconductance was 10 mS from obserbed DC charactarisrtics.To reduce scattering of electron, purity of InP intrinsic layer was confirmed. As a result, electron mobility of 110,000 cm^2/Vs at 77 K was confirmed in AlInAs/InP HEMT structure, When Si-doped layer was eliminated, electron mobility of 220,000 cm^2/Vs at 77K was confirmed. To our knowledge, these mobility at 77K was world records. Thus high purity of our materials was confirmed.2.Collector structure by buried nano-metal-wire.Through study through crystal growth, we found that thickness of over layer on wires was changed by the number of wires. Because failure of crystal growth was due to this phenomena, we fabricated the structure with only one wire as a collector with refinement of crystal growth conditions. As a result, we fabricated HBT with one nano^metal wire as collector. In this device, the emitter area was 0.1μm×0.5μm. To our knowledge, this area was smallest as heterojunction bipolar transistors. Smallest total collector capacitance was also confirmed.As a contact resistance, emitter contact resistivity was reduced from 3x10^<-6>Wcm^2 to 1x10^<-6>Wcm^2 and base contact resistivity was reduced from 2.5x10^<-6>Wcm^2 to 3x10^<-7>Wcm^2 by change of electrode material (from titanium to pallsdium). This reduction combined with small collector capacitance is very important to obtain good microwave performance.
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Keigo Yokoyama: "Fabrication of GaInAs/InP heterojunction bipolar transistors with a single tungsten wire as collector electrode"Jpn.J.Appl.Phys.. 42・12B. L1051-L1503 (2003)
Keigo Yokoyama:“用单根钨丝作为集电极电极的 GaInAs/InP 异质结双极晶体管的制造”Jpn.J.Appl.Phys.. 42・12B (2003)。
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通讯作者:
K.Takeuchi: "InP hot electron transistors using modulation of gate electrodes"The 2003 International Conference on Solid State Devices and Materials. E-7-3. (2003)
K.Takeuchi:“使用栅电极调制的 InP 热电子晶体管”2003 年国际固态器件和材料会议。
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K.Yokoyama: "Wet etching for self-aligned 0.1-mm-wide emitter in InP/InGaAs HBT"Topical Workshop on Heterostructure Microelectronics (TWHM'03). W-11. (2003)
K.Yokoyama:“InP/InGaAs HBT 中自对准 0.1 毫米宽发射极的湿法蚀刻”异质结构微电子专题研讨会 (TWHM03)。
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Y.Miyamoto: "InP Hot Electron Transistor with a Buried Metallic Gate for Electron Emission"60th Annual Device Research Conference. III-20. (2002)
Y.Miyamoto:“具有用于电子发射的埋入金属栅极的 InP 热电子晶体管”第 60 届年度器件研究会议。
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通讯作者:
R.Nakagawa: "InP Hot Electron Transistors with Reduced Emitter Width for Controllability of Collector Current by Gate Bias"International Conference on Indium Phosphide and Related Materials. P1-14. (2004)
R.Nakakawa:“InP热电子晶体管,具有减小的发射极宽度,可通过栅极偏置控制集电极电流”,磷化铟及相关材料国际会议。
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共 14 条
Complementary vertical tunnel FET aiming for low voltage and high speed operation by heterostructure design and miniaturization
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批准号:26249046
-
项目类别:Grant-in-Aid for Scientific Research (A)
-
资助金额:$26.54万
-
财政年份:2014
-
负责人:MIYAMOTO Yasuyuki
-
依托单位:
Research on vertical InP-related hot electron transistors with insulated gate
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批准号:19206038
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项目类别:Grant-in-Aid for Scientific Research (A)
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资助金额:$26.21万
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财政年份:2007
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负责人:MIYAMOTO Yasuyuki
-
依托单位:
Research for ultra-fast operation of InP HBT by ballistic transportation in collector
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批准号:16360170
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$9.54万
-
财政年份:2004
-
负责人:MIYAMOTO Yasuyuki
-
依托单位:
Improving Crystal Conditions of Compound Semiconductors Laterally Grown on Metal Wire
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批准号:11450006
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$8.83万
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财政年份:1999
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负责人:MIYAMOTO Yasuyuki
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依托单位:
Ultra High-Speed Operation of Ultra-Fine GaInAs/InP HBT by Suppressing Recombination Current at Mesa Sidewall
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批准号:11555092
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$8.19万
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财政年份:1999
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负责人:MIYAMOTO Yasuyuki
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依托单位:
海外基金