Void Formation Mechanisms in Cu Interconnect for Ultra Fast ULSI Application

铜薄膜已被用作先进半导体器件的互连材料。众所周知，在热加工过程中形成的空洞会导致互连失效。本文的工作重点是了解Cu/Ta/SiO_2/Si多层样品中的空洞形成机制。SEM和TEM观察表明，在<111>的强织构膜中存在孔洞，而在随机织构膜中没有孔洞。在孪晶的边角处、孪晶与其他孪晶的交点处或与晶界的交点处也有孔洞形成。为了了解孪晶的作用，采用三维有限元法（FEM）计算机程序对应力分布进行了模拟。利用电子衍射分析了实际样品的局部晶体学信息，并将其纳入有限元模拟。结果表明，Cu具有较大的弹性各向异性，导致双拐角和交叉处的应力集中，成为孔隙形成的驱动力。孪晶面取向分析表明<111>织构膜含有非相干{322}孪晶。具有高能量，而随机纹理薄膜包含具有低能量的相干孪晶。前一种双胞胎被发现是排尿的对象。在压力集中下。控制薄膜厚度和初始织构，可形成<100>取向的巨晶粒。由于孪晶在薄膜中不存在，因此在热加工过程中没有形成空洞。在大马士革线中，在沟槽开口的肩部形成了裂缝状的空洞。应力模拟结果表明，剪切应力集中导致Cu/Ta界面部分分层形成孔洞。这些结果表明，提高Cu/Ta界面的粘附强度对器件的可靠性至关重要。

Cu thin films have been used for an interconnect material for advanced semiconductor devices. Void formation during thermal processing has been known to cause interconnect failure. This work has focused on understanding the void formation mechanism in Cu/Ta/SiO_2/Si multilayer samples. SEM and TEM observation indicated that voids were formed in a strongly <111> textured film but not in a ramdom texture film. It was also found that the voids were formed at corners of twins and at intersections between twins with other twins or with grain boundaries. In order to understand the role of twins, stress distribution was simulated using a three dimensional finite element method (FEM) computer code. Localized crystallographic information of actual samples was analyzed with electron diffraction and was, incorporated in the FEM simulation. The results indicated that a large elastic anisotropy of Cu gave rise to stress concentration at twin corners and intersections that acted as a driving force for void formation. Orientation analysis of twin planes indicated that the <111> texture film contained incoherent {322} twins.having a high energy, while the random textured film contained coherent {111} twins having a low energy. The former twin of the {322} type was found to be subject voiding. under stress concentration. When the film thickness and the initial texture are controlled, <100> oriented giant grains could be formed. Since the twins were absent in this film, no void was formed during thermal processing In damascene lines, slit-like voids were formed at the shoulder of the trench opening. Stress simulation indicated that shear stress concentration caused the void formation by partial delamination at the Cu/Ta interface. These results suggested that the improvement of adhesion strength at the Cu/Ta interface is important for the device reliability.