Void Formation Mechanisms in Cu Interconnect for Ultra Fast ULSI Application

Cu薄膜已被用于先进半导体器件的互连材料。已知热处理期间的空隙形成会导致互连失效。本工作主要研究了Cu/Ta/SiO_2/Si多层膜样品中空洞的形成机理。扫描电镜和透射电镜观察表明，强织构薄膜中有孔洞形成<111>，而无规织构薄膜中没有孔洞形成。同时还发现，空洞形成于孪晶的角部以及孪晶与其他孪晶或与晶界的相交处。为了理解孪晶的作用，使用三维有限元法（FEM）计算机代码模拟应力分布。用电子衍射分析了实际样品的局部晶体学信息，并将其纳入有限元模拟。结果表明，铜的大的弹性各向异性引起应力集中在双角和交叉点，作为驱动力的空洞形成。孪晶面的取向分析表明，<111>织构膜包含具有高能量的非相干{322}孪晶，而随机织构膜包含具有低能量的相干{111}孪晶。发现{322}型的前一个双胞胎受试者排尿。在应力集中下。通过控制薄膜厚度和初始织构，<100>可以形成取向的巨晶粒。由于在该膜中不存在孪晶，因此在热处理期间没有形成空隙。在沟槽中，在沟槽开口的肩部处形成狭缝状空隙。应力模拟结果表明，切应力集中导致Cu/Ta界面局部脱层形成空洞。这些结果表明，在Cu/Ta界面处的粘附强度的改善是重要的器件的可靠性。

Cu thin films have been used for an interconnect material for advanced semiconductor devices. Void formation during thermal processing has been known to cause interconnect failure. This work has focused on understanding the void formation mechanism in Cu/Ta/SiO_2/Si multilayer samples. SEM and TEM observation indicated that voids were formed in a strongly <111> textured film but not in a ramdom texture film. It was also found that the voids were formed at corners of twins and at intersections between twins with other twins or with grain boundaries. In order to understand the role of twins, stress distribution was simulated using a three dimensional finite element method (FEM) computer code. Localized crystallographic information of actual samples was analyzed with electron diffraction and was, incorporated in the FEM simulation. The results indicated that a large elastic anisotropy of Cu gave rise to stress concentration at twin corners and intersections that acted as a driving force for void formation. Orientation analysis of twin planes indicated that the <111> texture film contained incoherent {322} twins.having a high energy, while the random textured film contained coherent {111} twins having a low energy. The former twin of the {322} type was found to be subject voiding. under stress concentration. When the film thickness and the initial texture are controlled, <100> oriented giant grains could be formed. Since the twins were absent in this film, no void was formed during thermal processing In damascene lines, slit-like voids were formed at the shoulder of the trench opening. Stress simulation indicated that shear stress concentration caused the void formation by partial delamination at the Cu/Ta interface. These results suggested that the improvement of adhesion strength at the Cu/Ta interface is important for the device reliability.