Void Formation Mechanisms in Cu Interconnect for Ultra Fast ULSI Application

用于超快速 ULSI 应用的铜互连中的空洞形成机制

• 批准号: 13450281
• 负责人: KOIKE Junichi
• 金额: $ 5.7万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2001
• 资助国家: 日本
• 起止时间: 2001 至 2003
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-13450281/
• 关键词: Cu; Interconnect; Void; Thermal stress; ULSI; Reliability; Anisotropy; 薄膜

Cu thin films have been used for an interconnect material for advanced semiconductor devices. Void formation during thermal processing has been known to cause interconnect failure. This work has focused on understanding the void formation mechanism in Cu/Ta/SiO_2/Si multilayer samples. SEM and TEM observation indicated that voids were formed in a strongly <111> textured film but not in a ramdom texture film. It was also found that the voids were formed at corners of twins and at intersections between twins with other twins or with grain boundaries. In order to understand the role of twins, stress distribution was simulated using a three dimensional finite element method (FEM) computer code. Localized crystallographic information of actual samples was analyzed with electron diffraction and was, incorporated in the FEM simulation. The results indicated that a large elastic anisotropy of Cu gave rise to stress concentration at twin corners and intersections that acted as a driving force for void formation. Orientation analysis of twin planes indicated that the <111> texture film contained incoherent {322} twins.having a high energy, while the random textured film contained coherent {111} twins having a low energy. The former twin of the {322} type was found to be subject voiding. under stress concentration. When the film thickness and the initial texture are controlled, <100> oriented giant grains could be formed. Since the twins were absent in this film, no void was formed during thermal processing In damascene lines, slit-like voids were formed at the shoulder of the trench opening. Stress simulation indicated that shear stress concentration caused the void formation by partial delamination at the Cu/Ta interface. These results suggested that the improvement of adhesion strength at the Cu/Ta interface is important for the device reliability.

铜薄膜已被用作先进半导体器件的互连材料。已知在热处理过程中形成空洞会导致互连故障。本工作主要研究了Cu/Ta/SiO_2/Si多层膜样品中空穴的形成机制。扫描电子显微镜和透射电子显微镜观察表明，在强织构的薄膜中形成空洞，而在无规则织构的薄膜中没有空洞形成。还发现空洞形成在孪晶的拐角处、孪晶与其他孪晶的交界处或晶界处。为了了解孪晶的作用，使用三维有限元计算机程序模拟了应力分布。用电子衍射仪分析了实际样品的局域结晶学信息，并将其纳入有限元模拟。结果表明，铜具有较大的弹性各向异性，在孪角和交叉处产生应力集中，是空洞形成的驱动力。孪晶面取向分析表明，&lt；111&gt；织构薄膜含有能量较高的非共格{322}孪晶，而随机织构薄膜含有能量较低的共格{111}孪晶。前一对双胞胎的{322}类型被发现为排尿。在应力集中的情况下。当控制薄膜厚度和初始织构时，可以形成&lt；100&gt；取向的巨晶。由于这种薄膜中没有孪晶，所以在热处理过程中没有在大马士革纹线上形成空洞，而是在沟槽开口的肩部形成了狭缝状的空洞。应力模拟表明，剪切应力集中导致了铜/钽界面部分分层空洞的形成。这些结果表明，提高铜/钽界面的结合强度对器件的可靠性是重要的。

项目成果

関口貴子, 小池淳一: "The effects of internal variables on interfacial debond strength on Cu/Ta/SiO_2/Si multilayers by nanoscratch test"MRS Symp.Proc.. (in press). (2004)

Takako Sekiguchi、Junichi Koike：“通过纳米划痕测试，内部变量对 Cu/Ta/SiO_2/Si 多层膜界面脱粘强度的影响”MRS Symp.Proc.（出版中）。

関口 貴子: "Microstructural influences on stress migration in electroplated Cu metallization"Applied Physics Letters. 83. 1962-1964 (2003)

Takako Sekiguchi：“电镀铜金属化中应力迁移的微观结构影响”《应用物理快报》83。1962-1964（2003）

関口貴子: "Formation of Slit-Like Voids at Trench Corners of Damascene Cu Interconnects"Materials Transactions. 43. 1633-1637 (2001)

Takako Sekiguchi：“在大马士革铜互连线的沟槽角处形成狭缝状空隙”材料交易 43. 1633-1637 (2001)。

Atsuko, SEKIGUCHI: "Void formation by thermal stress concentration at twin interfaces in Cu thin films"Applied Phisics Letters. 79. 1264-1266 (2001)

Atsuko, SEKIGUCHI：“铜薄膜孪晶界面处的热应力集中导致空隙形成”应用物理学快报。

小池 淳一: "A Relationship between Film Texture and Stress Voiding Tendency in Copper Thin Films"AIP Conf. Proc.. 印刷中. (2002)

Junichi Koike：“铜薄膜中薄膜纹理与应力空洞倾向之间的关系”AIP 会议论文集（2002 年）。