Coupled Hybrid Bandwidth Peaking Techniques for BiCMOS Multiplexer and Demultiplexer Beyond 200 Gb/s (PEAK)

未来将需要运行速度超过100gb /s的通信系统。为了实现这样的超高数据速率，可以使用多路复用器（MUX）和解路复用器（DMUX）电路以较低的速度将数据分割成多个并行流。在BiCMOS中，已经发布了数据速率高达180 Gb/s的MUX ic和数据速率高达100 Gb/s的DMUX ic。为了达到最大速度，需要电感带宽峰值技术。最常见的是采用串联、分流或t线圈调峰方法，这些方法能够分别将带宽提高1.4、1.7和2.8倍。PEAK希望将BiCMOS中MUX和DMUX的技术水平提高到200gb /s以上。锁存器同步将包括在内。t型线圈主要使用提供远低于200 GHz的自共振频率（srf）的耦合螺旋电感来实现。因此，它们不适合PEAK。我们研究了一种新型的基于传输线的t型线圈，其工作频率远高于200ghz。t型线圈的峰值利用了线圈间的强耦合。然而，在200 GHz左右，耦合线的长度与线距之间的比率很低。这将导致较小的耦合因子，从而降低峰值的效率。我们想研究如何在保持高srf的同时最大化线圈耦合。此外，我们还研究了如何优化具有中等t线圈耦合的ic，例如通过添加极和串联和/或并联峰值的智能组合。这些高阶调峰方法通过在级联电路块的输入、中间和输出节点上的异构调峰方法的智能分布得到扩展。为了深入理解势和极限，推导了方程。除了带宽，我们还研究了阶跃响应，时钟和数据信号的抖动以及组延迟方面的权衡，最终允许大的开口。将考虑包装的寄生性。可选地，我们还研究了多相架构来放松锁存器的速度。为了验证这些方法，在最快的IHP BiCMOS技术上实现了MUX和DMUX演示ic。我们的初步模拟预测MUX和DMUX速度超过200gb /s应该是可能的。该电路将应用于两种应用：第一，作为更快的通信系统的实现器，第二，扩展我们的MORE测量平台，该平台可以由第三方用户进行评估。例如，我们最先进的SHF误码率测试仪（BERT），即使采用非归零（NRZ）调制，也能够测量每条路径高达120 Gb/s的电路。通过使用PEAK MUX和DMUX应用两条路径，我们可以将MORE-BERT扩展到每条路径200 Gb/s的创纪录速度。这也将有利于由6所德国大学的12位主席组成的MORE合作伙伴。因此，匹克加强了德国研究界设计最快的集成电路。

Communication systems operating beyond 100 Gb/s will be required in the future. To enable such ultra-high data rates, the data can be split in multiple parallel streams with lower speed using multiplexer (MUX) and demultiplexer (DMUX) circuits. In BiCMOS, MUX ICs with data rates up to 180 Gb/s and DMUX ICs up to 100 Gb/s were published. To reach maximum speeds, inductive bandwidth peaking techniques are required. Most frequently, series, shunt or T-coil peaking approaches are applied, which are capable to improve the bandwidth by factors up to 1.4, 1.7 and 2.8, respectively. PEAK wants to push the state of the art of MUX and DMUX in BiCMOS beyond 200 Gb/s. Latches for synchronisation will be included. T-coils are mainly realised using coupled spiral inductors providing self-resonance frequencies (SRFs) well below 200 GHz. Hence, they are not suited for PEAK. We investigate novel transmission-line-based T-coils capable to operate well beyond 200 GHz. T-coil peaking exploits strong mutual coil coupling. However, around 200 GHz, the ratio between the length of the coupled lines and the line distances is low. This leads to smaller coupling factors and hence less efficient peaking. We want to investigate how the coil coupling can be maximised while keeping the SRFs high. Furthermore, we study how ICs with moderate T-coil coupling can be optimised, e.g. by adding of poles and smart combination with series and/or shunt peaking. These higher order peaking methods are extended by smart distribution of heterogeneous peaking approaches at the input, intermediate and output nodes of cascaded circuit blocks. To deeply understand the potentials and limits, equations are derived. In addition to the bandwidth, we investigate also trade-offs with respect to the step response, jitter of the clock and data signals and group delay, to finally allow large eye-openings. The packaging parasitics will be taken into account. Optionally, we investigate also multi-phase architectures to relax the speed of the latches. To verify the approaches, MUX and DMUX demonstrator ICs are realised in the fastest IHP BiCMOS technology. Our preliminary simulations predict that MUX and DMUX speeds beyond 200 Gb/s should be possible. The circuits will be applied for 2 applications: First, as enabler for faster communication systems, and second, to extend our MORE measurement platform, which can be assessed by third party users. MORE includes e.g. our state-of-the-art SHF bit-error-rate-tester (BERT), which is capable to measure circuits up to 120 Gb/s per path even with non-return-to-zero (NRZ) modulation. By applying two paths using the PEAK MUX and DMUX, we can extend the MORE-BERT towards a record speed of 200 Gb/s per path. This will also be beneficial for the MORE partners consisting of 12 chairs from 6 German universities. Hence, PEAK strengthens the German research community to design fastest ICs.