Development of Educational Microprocessors for Computer Science Education
Development of Educational Microprocessors for Computer Science Education
批准号:
06558043
负责人:
YASUURA Hiroto
金额:
$11.58万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
财政年份:
1994
资助国家:
日本
项目状态:
已结题
起止时间:
1994 至 1995
中文摘要
目前的大学和高等教育机构的计算机教育课程强调计算机知识和编程,它不足以理解计算机系统的全貌,从软件到硬件,以及计算机制的原理。本课题旨在开发适合计算机科学教育的微处理器系统,并利用这些教育微处理器设计计算机系统系统教育的课程课程。我们的成果总结如下:1.32位RISC教育微处理器:我们开发了QP-DLX(九州大学)和DLX-FPGA(九州工业大学);这两种微处理器都具有现代架构,如32位RISC、指令管道和异常处理。它们还具有教育特性,例如处理器内部状态的可观察性。FPGA教育微处理器:FPGA是一种可重构器件,可用于在教室中实现学生设计的微处理器。我们为不同的教育水平开发了几种FPGA微处理器板。DLX-FPGA是一种适合研究生微处理器设计项目的32位微处理器,并针对使用硬件描述语言的设计课程开发了基于DLX-FPGA的模型课程。PICO(庆应义塾大学)适合入门级计算机教育,其课程考虑到班级中大量学生的使用。公开发布设计数据和基准:本项目开发的各种设计数据、文档和课程文本,以及CAD基准,将通过互联网发布给公众使用。
英文摘要
Current computer education curricula of universities and higher educational institutes put emphasis on computer literacy and programming, and it is not sufficient for understanding the total picture of computer systems, from software to hardware, and principles of computing mechanisms. This research project is aimed at developing microprocessor systems suitable for education of computer science, and designing course curricula for systematic education of computer systems, utilizing those educational microprocessors. Our achievements are summarized below :1.32-bit RISC educational microprocessors : We have developed QP-DLX (Kyushu Univ.) and DLX-FPGA (Kyushu Inst. Tech.) ; both microprocessors have modern architectures such as 32-bit RISC, instruction pipeline, and exception handling. They also have educational features such as observability of internal processor states.2. FPGA educational microprocessors : FPGA is a reconfigurable device and it can be used for implementing student-designed microprocessors in classrooms. We have developed several FPGA microprocessor boards for different education levels. DLX-FPGA is a 32-bit microprocessor suitable for graduate microprocessor design projects, and a model curriculum using DLX-FPGA is also developed for design courses using hardware description languages. PICO (Keio Univ.) is suitable for entry-level computer education and its curriculum takes account of use in classes of a large number of students.3. Public release of design data and benchmarks : Various design data, documents, and course texts developed in this project, together with CAD benchmarks, are released for public use through the Internet.
期刊论文(20)
专著(0)
科研奖励(0)
会议论文
登录
查看更多内容
T.Sueyoshi, H.Inoue, et al.: ""Development of Educational 32-bit RISC Microprocessor DLX-FPGA and its Processor Board, "" Proc.3rd FPGA/PLD Conference & Exhibit. 579-595 (1995)
T.Sueyoshi、H.Inoue 等人:“教育用 32 位 RISC 微处理器 DLX-FPGA 及其处理器板的开发”,Proc.3rd FPGA/PLD 会议
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
A.Hirata, H.Onodera, and K.Tamaru: ""Estimation of Short Circuit Power Dissipation for Static CMOS Gates, "" IEICE Trans.Fundamentals. Vol.E79-A, No.3. (1996)
A.Hirata、H.Onodera 和 K.Tamaru:“静态 CMOS 门的短路功耗估计”,IEICE Trans.Fundamentals。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
末吉敏則、井上弘士 他: "教育用32ビットRISCマイクロプロセッサDLX-FPGAと教育ボードの開発" 第3回FPGA/PLD Conference & Exhibit論文集. 579-595 (1995)
Toshinori Sueyoshi、Hiroshi Inoue 等人:“教育型 32 位 RISC 微处理器 DLX-FPGA 和教育板的开发”第三届 FPGA/PLD 会议暨展览论文集 579-595 (1995)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
H.Kambara, and H.Yasuura: ""KUE-CHIP2 : A Microprocessor for Education of LSI Design, "" Proc.Synthesis and System Integration of Mixed Technologies (SASIMI '95). 233-240 (1995)
H.Kambara 和 H.Yasuura:“KUE-CHIP2:用于 LSI 设计教育的微处理器”,混合技术的 Proc.Synthesis 和系统集成 (SASIMI 95)。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
M.Okumura, N.Yokoo, et al.: ""Design and Implementaion of the Educational Microprocessor KITE using Gate Array with Full Synthesis, "" Proc.SASIMI '95. 219-226 (1995)
M.Okumura、N.Yokoo 等人:“使用全合成门阵列设计和实现教育微处理器 KITE”,Proc.SASIMI 95。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
共 16 条
Research on Design Methodology of Dependable LSI Loading Value and Trust
-
批准号:19200004
-
项目类别:Grant-in-Aid for Scientific Research (A)
-
资助金额:$30.45万
-
财政年份:2007
-
负责人:YASUURA Hiroto
-
依托单位:
Development of High-performance Low-power Processor Systems
-
批准号:13023208
-
项目类别:Grant-in-Aid for Scientific Research on Priority Areas
-
资助金额:$40.32万
-
财政年份:2000
-
负责人:YASUURA Hiroto
-
依托单位:
The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption
-
批准号:12558029
-
项目类别:Grant-in-Aid for Scientific Research (B)
-
资助金额:$8.51万
-
财政年份:2000
-
负责人:YASUURA Hiroto
-
依托单位:
A Study on Delay and Function Test for Core-Based System LSIs
-
批准号:11450143
-
项目类别:Grant-in-Aid for Scientific Research (B)
-
资助金额:$8.45万
-
财政年份:1999
-
负责人:YASUURA Hiroto
-
依托单位:
Research on Low-Power Design of Microprocessor Systems.
-
批准号:09480057
-
项目类别:Grant-in-Aid for Scientific Research (B)
-
资助金额:$8.38万
-
财政年份:1997
-
负责人:YASUURA Hiroto
-
依托单位:
Development of Curriculums for Education of VLSI System Design.
-
批准号:08558025
-
项目类别:Grant-in-Aid for Scientific Research (A)
-
资助金额:$12.67万
-
财政年份:1996
-
负责人:YASUURA Hiroto
-
依托单位:
Research on Performance Evaluation Technology for High-Performance Computer Systems
-
批准号:07458063
-
项目类别:Grant-in-Aid for Scientific Research (B)
-
资助金额:$4.74万
-
财政年份:1995
-
负责人:YASUURA Hiroto
-
依托单位:
Research on Logic Synthesis and Hardware Description Language Considering Layout Design
-
批准号:04452198
-
项目类别:Grant-in-Aid for General Scientific Research (B)
-
资助金额:$4.54万
-
财政年份:1992
-
负责人:YASUURA Hiroto
-
依托单位:
Research on High-Level Information Extraction in Integrated Circuit Design
-
批准号:02650264
-
项目类别:Grant-in-Aid for General Scientific Research (C)
-
资助金额:$1.86万
-
财政年份:1990
-
负责人:YASUURA Hiroto
-
依托单位: