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Research on Logic Synthesis and Hardware Description Language Considering Layout Design

考虑布局设计的逻辑综合与硬件描述语言研究

基本信息

批准号：
04452198
负责人：
YASUURA Hiroto
金额：
$ 4.54万
依托单位：
Kyushu Univ.
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1992
资助国家：
日本
起止时间：
1992 至 1993
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-04452198/
关键词：
VLSI CAD Placement and Routing, Hardware Description Language Hardware Software Codesign Login Synthesis Microprocessor Soft Core-Processor Layout Synthesis ソフトコアプロセッサレイアウト設計配線遅延

项目摘要

Traditional logic synthesis technology principally aims at generating topological information of logic circuits, realizing function given by functional description. Geometric information which appears in a final mask-pattern is decided in layout synthesis stage independently from logic synthesis. Therefore, in the case of random circuits like control-path, it is possible to get better performance than manual design. But, in the case of regular circuits like data-path, iti is hard to design good synthesis method in which geometric restriction on layout is considered in logic synthesis, and a design description language for that purpose.(a) Study on design description language that canrepresent regularity of layout-pattern : We proposed a language which can specigy the regularity on layout-pattern and the outline of placement and routing information in functional design.(b) Study on logic synthesis considering areas and wiring delays : We investigated a logic sythesis method considering wiring delays and areas in logic synthesis, and proposed a circuit synthesis method using the commutative law.(c) Comparisons of methods to design the practical circuits : We examined the effect of the several synthesis methods, applying them to practical development of a microprocessor. We concretely point out problems on commercial tools and languages.(d) Applocation of the logic synthesis method : As an application of our method, we propose hardware/software codesign using soft core-processor.Through the above researches, we unified logic synthesis and layout synthesis, which have been done independently. In our method, designers specify information on layout in architecture design, and logic synthesis and layout synthesis are done using its information. We also show a framework of new design automation system and its application method.

传统的逻辑综合技术主要是为了生成逻辑电路的拓扑信息，实现功能描述所给出的功能。出现在最终掩模图案中的几何信息是在版图综合阶段独立于逻辑综合而确定的。因此，在像控制路径这样的随机电路的情况下，有可能获得比人工设计更好的性能。但是，对于数据路径这样的规则电路，很难设计出在逻辑综合中考虑版图几何约束的好的综合方法和设计描述语言。(A)能够表示版图规则性的设计描述语言的研究：我们提出了一种能够描述版图规律性的语言，以及功能设计中布局和布线信息的轮廓。(B)考虑面积和布线延迟的逻辑综合研究：我们研究了逻辑综合中考虑布线延迟和面积的逻辑综合方法，并提出了一种基于交换律的电路综合方法。(C)实际电路设计方法的比较：我们考察了几种综合方法的效果，并将它们应用于微处理器的实际开发中。(D)逻辑综合方法的应用：作为该方法的一个应用，我们提出了软核处理器的软硬件协同设计方法，通过上述研究，我们将逻辑综合和版图综合统一起来，这两种综合已经独立完成。在该方法中，设计者在建筑设计中指定版图信息，并利用其信息进行逻辑综合和版图综合。给出了一种新的设计自动化系统的框架结构及其实现方法。