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Research on High-Level Information Extraction in Integrated Circuit Design

集成电路设计中高层信息提取研究

基本信息

批准号：
02650264
负责人：
YASUURA Hiroto
金额：
$ 1.86万
依托单位：
Kyoto University
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (C)
财政年份：
1990
资助国家：
日本
起止时间：
1990 至 1991
项目状态：
已结题

项目摘要

The goal of this research project is to establish a basic meibodology for functional infoffnadon extraction from logic circuits. The target problem is inverse transformation of logic synthesis. The obtained results of this research are summarized as follows :1. We developed a method to extract furiclional information from combinational logic circuits. In this method, we use a Binary Decision Diagram(BDD)as a basic data structure. We also use additional information added to a net list of a logic circuit. The additional information consists of types of signal lines and coding scheme of numerical data and characters. Using the additional information. we can extract arithmetic functions like addition or multiplication, as well as logical operations. Our approach is independent from structure of a circuit from which functional information is extracted. We developed a prototype system of functional information extraction, called FINES, and extend the method to functional information extraction from sequential circuits.2. We developed a system to extract functional information from descriptions of transister level circuits. Combining the established technology to extract circuits from layout information, we can develop a system to extract functional information from layout descriptions. This method is independent from libraries of logic elements.3. We discussed applications of the functional information extraction technique to automatic generation of functional simulation models, design verification, test generation and computer aided documentation.All the above results have been published or presented in journals, international conferences and workshops. The methodology developed in the research can be applied to analog circuits and software engineering area. The fundamental problem of fundonal information extraction is recognition of the function or behavior from static descriptions. This seems to be one of the basic problems of inforinadon sciences.

该研究项目的目标是建立从逻辑电路中提取功能信息的基本方法学。目标问题是逻辑综合的逆变换。本研究取得的成果概括如下： 1．我们开发了一种从组合逻辑电路中提取字符信息的方法。在该方法中，我们使用二元决策图（BDD）作为基本数据结构。我们还使用添加到逻辑电路的网表中的附加信息。附加信息包括信号线的类型以及数字数据和字符的编码方案。使用附加信息。我们可以提取算术函数，例如加法或乘法，以及逻辑运算。我们的方法独立于从中提取功能信息的电路结构。我们开发了功能信息提取原型系统FINES，并将该方法扩展到时序电路的功能信息提取。 2．我们开发了一个系统，可以从晶体管级电路的描述中提取功能信息。结合现有的从布局信息中提取电路的技术，我们可以开发一个从布局描述中提取功能信息的系统。该方法独立于逻辑元件库。 3．我们讨论了功能信息提取技术在功能仿真模型自动生成、设计验证、测试生成和计算机辅助文档方面的应用。所有上述结果均已在期刊、国际会议和研讨会上发表或展示。研究中开发的方法可应用于模拟电路和软件工程领域。基本信息提取的根本问题是从静态描述中识别功能或行为。这似乎是信息科学的基本问题之一。