A Study on Delay and Function Test for Core-Based System LSIs

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Recent significant advances in LSI technologies have been increasing the number of transistors on a chip dramatically. System designers can now build a large system on a single chip as a system-on-a-chip (SOC). They often use multiple pre-designed and pre-verified blocks to reduce the time required for design and verification. These cores include black-boxed cores whose details are unknown due to the protection of intellectual property (IP) information. The importance of testing the function and performance has been increasing as the LSI technologies have been increasing.We proposed function and performance test methods for Core-Based System LSIs. We proposed a function test method named as CBET (Combination of BIST and External Test) scheme. We theoretically and experimentally validated that the CBET scheme can reduce much testing time. We also proposed a performance test method in which the delay time at a node is treated stochastically. This method can reduce extra margins of the delay time and therefore can estimate the performance for LSIs accurately.