Development of High-performance Low-power Processor Systems

高性能低功耗处理器系统的开发

• 批准号: 13023208
• 负责人: YASUURA Hiroto
• 金额: $ 40.32万
• 依托单位: kyushu University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research on Priority Areas
• 财政年份: 2000
• 资助国家: 日本
• 起止时间: 2000 至 2002
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-13023208/
• 关键词: High-performance Low-power; Datapath width optimization; Dynamic control of pipeline depth; Dynamic control of data-bus; Dynamic control of memory access bits; 低消費電力プロセッサ; 可変電源電圧プロセッサ; 有効ビット幅解析; 動的データパス幅制御; 動的メモリアクセスビット幅制御; システムLSI; プロセッサ; 高性能

In this research, we aim to develop constructing techniques for high-performance low-power processor systems, which combine software, architecture and circuit techniques such as processor and memory architectures, voltage control, and hardware software co-design. Although voltage, datapath width, and pipeline depth are not available in the past, we provide use of these parameters for designers of application-specific processor systems. In other words, this research is trying to provide means for designing high effective systems in large design space. This approach is the most progressive one in hardware software co-design techniques that have been researched and developed competitively in countries. We think that it is important to give these guidelines designers of application-specific processor systems. Proposed techniques can be summarized as follows1)After analyzing the minimum bitwidth (effective bitwidth) for variables in programs, the datapath width is optimized for power efficiency processors or memories by using effective bitwidth.2)The pipeline depth is dynamically controlled in consideration of characteristics of applications for low power.3)Data bus and memory access bits are dynamically controlled to suppress power consumption of bits not transferring necessary information in datapath.

在这项研究中，我们的目标是开发高性能低功耗处理器系统的构建技术，该系统结合了软件、架构和电路技术，例如处理器和内存架构、电压控制和硬件软件协同设计。尽管电压、数据路径宽度和流水线深度在过去不可用，但我们为特定应用处理器系统的设计人员提供了这些参数的使用。换句话说，这项研究试图为在大设计空间中设计高效系统提供手段。该方法是目前各国竞相研发的软硬件协同设计技术中最先进的一种。我们认为为特定应用处理器系统的设计者提供这些指导非常重要。所提出的技术可概括如下：1）分析程序中变量的最小位宽（有效位宽）后，通过使用有效位宽，针对处理器或存储器的能效优化数据路径宽度。2）考虑低功耗应用的特性，动态控制流水线深度。3）动态控制数据总线和存储器访问位，以抑制不需要传输的位的功耗。 数据路径中的信息。

项目成果

Yun Cao, Hiroto Yasuura: "Low-Energy Design Using Datapath Width Optimization for Embedded Processor-Based Systems"IPSJ Jornal. 43・5. 1348-1359 (2002)

Yun Cao、Hiroto Yasuura：“使用基于嵌入式处理器的系统的数据路径宽度优化的低能耗设计” IPSJ 杂志 43・5 (2002)。

M.Mesbah Uddin, Yun Cao, Hiroto Yasuura: "An Accelerated Datapath Width Optimization Technique for Area Reduction of Embedded Systems"Proc. of IEEE/ACM International Symposium on System Synthesis. 2002. (2002)

M.Mesbah Uddin、Yun Cao、Hiroto Yasuura：“一种用于减少嵌入式系统面积的加速数据路径宽度优化技术”Proc。

Yun Cao, Hiroto Yasuura: "Video Quality Modeling for Quality-driven Design"The 10th Workshop on System And System Integration of Mixed Technologies(SASIMI 2001). 86-92 (2001)

Yun Cao、Hiroto Yasuura：“质量驱动设计的视频质量建模”第十届系统和混合技术系统集成研讨会（SASIMI 2001）。

T.Okuma, T.Ishihara, H.Yasuura: "Software Energy Reduction Techniques for Variable Voltage Processors"IEEE Design & Test of Computers. Vol.18, No.2. 31-41 (2001)

T.Okuma、T.Ishihara、H.Yasuura：“可变电压处理器的软件节能技术”IEEE Design

T.Yamada, S.Goto, N.Takayama, Y.Matsushita, Y.Harada, H.Yasuura: "Low-Power Architecture of Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems"IEICE Transactions on Electronics. E86-C No.1. 79-88 (2003)

T.Yamada、S.Goto、N.Takayama、Y.Matsushita、Y.Harada、H.Yasuura：“用于直接序列扩频系统的数字匹配滤波器的低功耗架构”IEICE Transactions on Electronics。