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The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption

面向低能耗的变压处理器基础软件技术开发

基本信息

批准号：
12558029
负责人：
YASUURA Hiroto
金额：
$ 8.51万
依托单位：
Kyushu University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2000
资助国家：
日本
起止时间：
2000 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-12558029/
关键词：
Low Energy System on a Chip Variable Voltage Embedded System System Software Processor Architecture Memory

项目摘要

This work discusses some basic techniques of software for variable-voltage processors in order to realize low-energy design, together with modeling techniques and evaluations of their potential benefits by simulation. Details are listed as follows :1) A task scheduling technique for a real-time system with a variable-voltage processor, by which supply voltage is changed dynamically, is presented.2) A platform for datapath width optimization of soft-core processors is built and the presented methodology of datapath optimization is evaluated by using MPEG AAC decoder. In addition, an energy minimization methodology using datapath width optimization is proposed. To find the optimized datapath width for a given application in the early phase of designs, an effective bitwidth and access frequency of variables based performance estimation technique is also developed. A low-energy memory design technique is presented as well.3) A new datapath width optimization methodology considering computation precision targeting area and power reduction is presented.4) A power reduction technique by reducing switching of redundant bit is presented, here effective bit line on data bus is called active bit, the other bit is called redundant bit.5) A cost model for SoC (System on a Chip), in which each cost as a parameter is presented, and a design method by market scale and number of products is also presented.6) High-performance/low power cache architectures with variable cache-line size for merged DRAM/Logic LSIs are presented ; in addition, a low-power instruction cache architecture exploiting program execution footprints is presented.

这项工作讨论了一些基本的软件技术，以实现低功耗设计的可变电压处理器，连同建模技术和评估其潜在的好处，通过仿真。具体内容如下：1）提出了一种基于可变电压处理器的实时系统任务调度技术，通过该技术实现了电源电压的动态变化; 2）搭建了一个软核处理器数据路径宽度优化平台，并利用MPEG AAC解码器对所提出的数据路径优化方法进行了评估。此外，能量最小化的方法，使用数据路径宽度优化。为了在设计的早期阶段为给定的应用程序找到最佳的数据路径宽度，还开发了一种基于有效位宽和访问频率的性能估计技术。3）提出了一种兼顾计算精度和功耗降低的数据路径宽度优化方法; 4）提出了一种通过减少冗余位的切换来降低功耗的方法，其中数据总线上的有效位线称为有效位，其余位称为冗余位; 5）提出了一种SoC的成本模型（片上系统），其中每个成本作为一个参数，并根据市场规模和产品数量的设计方法也被提出。6）高性能/低功耗的高速缓存架构与可变的高速缓存线大小合并DRAM/逻辑LSI提出了，此外，低功耗的指令高速缓存架构利用程序执行足迹。