Research on Low-Power Design of Microprocessor Systems.

我们提出了利用lsi特性的低功耗微处理器系统的新设计技术。本研究涵盖处理器与记忆体的低功耗架构、降低功耗的最佳电源电压控制策略，以及低功耗设计的硬件/软件协同设计技术。得到了以下结果：1)开发具有可变电压处理器架构的低功耗系统：在这种架构中，我们提供了几个电源电压水平和对应于每个电压水平的时钟频率。程序员可以根据程序所需的负载选择最佳电压水平。我们证明了一个选择最佳电压的基本定理，并实现了一个带有电压控制指令的原型处理器。在实际应用中，可实现70%以上的功耗降低。2)开发具有可变数据路径宽度的低功耗处理器：我们提出了一种新的处理器架构，其中活动数据路径宽度可以通过程序控制。该体系结构可以很容易地与基于软核处理器的软硬件协同设计技术相结合。3)减少总线转换的编译器技术和缓存存储器的低功耗设计技术：我们提出了一种编译器技术来控制总线上指令和数据的编码和传输顺序。我们还开发了一种降低功耗的方法，在这种方法中，指令和数据可以从缓存存储器中读取。4)逻辑-DRAM混合LSI的低功耗架构：对于逻辑-DRAM混合LSI的存储器层次，我们提出了一种减少DRAM刷新次数的技术，以最大限度地降低存储器系统的功耗。5)低功耗电路逻辑综合方法的发展：我们开发了一种新的逻辑综合算法，结合转导法生成最小功耗组合电路。

We proposed novel design techniques for low-power consumption microprocessor systems utilizing characteristics of LSIs. The research covers low-power architectures of processors and memories, an optimum control strategy of supply voltage for minimizing power consumption, and hardware/software codesign techniques for low-power design. The following results have been obtained.1) Development of low-power systems with a variable voltage processor architecture : In this architecture, we provide several supply voltage levels and clock frequency corresponding to each voltage level. Programmers can select the optimum voltage levels according to the required load of programs. We proved a basic theorem for the selection of the optimum voltage and implemented a prototype processor with a voltage control instruction. More than 70% power reduction is achieved for practical programs.2) Development of a low-power processor with variable data-path width : We proposed a new processor architecture in which active data-path width can be controlled from programs. This architecture can be easily combined with the hardware/software codesign technique based on Soft-core processor.3) A compiler technique for reducing bus transitions and a low-power design technique of cache memories : We proposed a compiler technique which controls coding and order of transfer of instructions and data on buses. We also developed a power reduction method in which instructions and data read from cache memory are expected.4) A low-power architecture of logic-DRAM mixed LSIs : For the memory hierarchy of logic-DRAM mixed LSI, we have proposed a. technique to reduce the number of refresh of DRAM to minimize the power consumption in the memory system.5) Development of logic synthesis method for low-power circuits : We developed a new logic synthesis algorithm combined with Transduction method to generate the power minimum combinational circuits.