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Research on Low-Power Design of Microprocessor Systems.

微处理器系统低功耗设计研究。

基本信息

批准号：
09480057
负责人：
YASUURA Hiroto
金额：
$ 8.38万
依托单位：
KYUSHU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1998
项目状态：
已结题

项目摘要

We proposed novel design techniques for low-power consumption microprocessor systems utilizing characteristics of LSIs. The research covers low-power architectures of processors and memories, an optimum control strategy of supply voltage for minimizing power consumption, and hardware/software codesign techniques for low-power design. The following results have been obtained.1) Development of low-power systems with a variable voltage processor architecture : In this architecture, we provide several supply voltage levels and clock frequency corresponding to each voltage level. Programmers can select the optimum voltage levels according to the required load of programs. We proved a basic theorem for the selection of the optimum voltage and implemented a prototype processor with a voltage control instruction. More than 70% power reduction is achieved for practical programs.2) Development of a low-power processor with variable data-path width : We proposed a new processor architecture in which active data-path width can be controlled from programs. This architecture can be easily combined with the hardware/software codesign technique based on Soft-core processor.3) A compiler technique for reducing bus transitions and a low-power design technique of cache memories : We proposed a compiler technique which controls coding and order of transfer of instructions and data on buses. We also developed a power reduction method in which instructions and data read from cache memory are expected.4) A low-power architecture of logic-DRAM mixed LSIs : For the memory hierarchy of logic-DRAM mixed LSI, we have proposed a. technique to reduce the number of refresh of DRAM to minimize the power consumption in the memory system.5) Development of logic synthesis method for low-power circuits : We developed a new logic synthesis algorithm combined with Transduction method to generate the power minimum combinational circuits.

我们提出了利用LSI特性的低功耗微处理器系统的新颖设计技术。该研究涵盖处理器和存储器的低功耗架构、用于最小化功耗的电源电压最佳控制策略以及用于低功耗设计的硬件/软件协同设计技术。取得了以下成果： 1)采用可变电压处理器架构的低功耗系统的开发：在该架构中，我们提供了几种电源电压级别以及与每个电压级别相对应的时钟频率。程序员可以根据所需的程序负载选择最佳的电压电平。我们证明了选择最佳电压的基本定理，并实现了带有电压控制指令的原型处理器。实际程序的功耗降低了70％以上。2）开发具有可变数据路径宽度的低功耗处理器：我们提出了一种新的处理器架构，其中可以通过程序控制活动数据路径宽度。该架构可以很容易地与基于软核处理器的硬件/软件协同设计技术相结合。3）减少总线转换的编译器技术和高速缓冲存储器的低功耗设计技术：我们提出了一种控制总线上指令和数据的编码和传输顺序的编译器技术。我们还开发了一种功耗降低方法，其中预计从高速缓冲存储器读取指令和数据。4）逻辑-DRAM混合LSI的低功耗架构：对于逻辑-DRAM混合LSI的存储器层次，我们提出了a。 5）开发低功耗电路的逻辑综合方法：我们开发了一种新的逻辑综合算法，结合Transduction方法来生成功耗最小的组合电路。