课题基金 / 基金详情

Research on Low-Power Design of Microprocessor Systems.

Research on Low-Power Design of Microprocessor Systems.
微处理器系统低功耗设计研究。
批准号:
09480057
负责人:
YASUURA Hiroto
金额:
$8.38万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
1997
资助国家:
日本
项目状态:
已结题
起止时间:
1997 至 1998

项目摘要

项目成果

YASUURA Hiroto的其他基金

相似基金

相关文献

中文摘要
翻译
点击翻译按钮获取中文摘要
英文摘要
We proposed novel design techniques for low-power consumption microprocessor systems utilizing characteristics of LSIs. The research covers low-power architectures of processors and memories, an optimum control strategy of supply voltage for minimizing power consumption, and hardware/software codesign techniques for low-power design. The following results have been obtained.1) Development of low-power systems with a variable voltage processor architecture : In this architecture, we provide several supply voltage levels and clock frequency corresponding to each voltage level. Programmers can select the optimum voltage levels according to the required load of programs. We proved a basic theorem for the selection of the optimum voltage and implemented a prototype processor with a voltage control instruction. More than 70% power reduction is achieved for practical programs.2) Development of a low-power processor with variable data-path width : We proposed a new processor architecture in which active data-path width can be controlled from programs. This architecture can be easily combined with the hardware/software codesign technique based on Soft-core processor.3) A compiler technique for reducing bus transitions and a low-power design technique of cache memories : We proposed a compiler technique which controls coding and order of transfer of instructions and data on buses. We also developed a power reduction method in which instructions and data read from cache memory are expected.4) A low-power architecture of logic-DRAM mixed LSIs : For the memory hierarchy of logic-DRAM mixed LSI, we have proposed a. technique to reduce the number of refresh of DRAM to minimize the power consumption in the memory system.5) Development of logic synthesis method for low-power circuits : We developed a new logic synthesis algorithm combined with Transduction method to generate the power minimum combinational circuits.
期刊论文(24)
专著(0)
科研奖励(0)
会议论文
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
Koji Kai, et al.: ""Analyzing and Reducing the Impact of Shorter Data Retention Time on the Performance of Merged DRAM/Logic LSIs, "" IEICE Trans.on Electronics. E81-C (9). 1448-1454 (1998)
Koji Kai 等人:“分析并减少较短数据保留时间对合并 DRAM/逻辑 LSI 性能的影响”,IEICE Trans.on Electronics。
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
Tohra Ishihara,et al: "Programmabie Power Management Architecfure for Power Reduction" IEICE Trans.on Electronics. E81-C(9). 1473-1480 (1998)
Tohra Ishihara 等人:“用于降低功耗的可编程电源管理架构”IEICE Trans.on Electronics。
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
22
    Research on Design Methodology of Dependable LSI Loading Value and Trust
    • 批准号:
      19200004
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $30.45万
    • 财政年份:
      2007
    • 负责人:
      YASUURA Hiroto
    • 依托单位:
    Development of High-performance Low-power Processor Systems
    • 批准号:
      13023208
    • 项目类别:
      Grant-in-Aid for Scientific Research on Priority Areas
    • 资助金额:
      $40.32万
    • 财政年份:
      2000
    • 负责人:
      YASUURA Hiroto
    • 依托单位:
    The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption
    • 批准号:
      12558029
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $8.51万
    • 财政年份:
      2000
    • 负责人:
      YASUURA Hiroto
    • 依托单位:
    A Study on Delay and Function Test for Core-Based System LSIs
    • 批准号:
      11450143
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $8.45万
    • 财政年份:
      1999
    • 负责人:
      YASUURA Hiroto
    • 依托单位:
    海外基金