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Research on Performance Evaluation Technology for High-Performance Computer Systems

Research on Performance Evaluation Technology for High-Performance Computer Systems
高性能计算机系统性能评估技术研究
批准号:
07458063
负责人:
YASUURA Hiroto
金额:
$4.74万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
1995
资助国家:
日本
项目状态:
已结题
起止时间:
1995 至 1996

项目摘要

项目成果

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中文摘要
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英文摘要
The purpose of this research is to develop a comprehensive technology for evaluating the performance, cost, and power consumption of high-performance computer systems. We have performed the following researches in particular.(a) Comprehensive performance evaluation on the compiler and the architecture for high-end microprocessors.(b) Developing and benchmarking the compiler, targetted for application-specific embedded microprocessors, which is enable to optimize the object-code according to the instruction-cache configurations.(c) Developing a modeling methodology for estimating the performance, area cost, and power consumption for "system-on-silicon" class VLSI,and then establishing a platform for evaluating tradeoff among these factors.(d) For parallel computer systems such as workstation-clusters and MPPs (Massively Parallel Processors) ;・Development of performance estimation models,・Study of quantitative evaluation index on scalability, and・Correlation analysis of benchmark programs.
期刊论文(24)
专著(0)
科研奖励(0)
会议论文
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通讯作者:
Satoko Sakata et al.: ""Performance Evaluation on a Work-station Cluster, TMC CM-5 and Intel Paragon Using a Parallel Homology Analysis Program"" Transactions of IPS Japan. vol.37, no.7. 1440-1450 (1996)
Satoko Sakata 等人:“使用并行同源分析程序对工作站集群、TMC CM-5 和 Intel Paragon 进行性能评估”,IPS Japan 交易。
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通讯作者:
坂田聡子 他: "ホモロジー解析プログラムを用いたワークステーションクラスタ,TMC CM-5,Intel Paragonの性能評価" 情報処理学会論文誌. 37. 1440-1450 (1996)
Satoko Sakata 等人:“使用同源分析程序对工作站集群、TMC CM-5、Intel Paragon 进行性能评估”日本信息处理学会汇刊 37. 1440-1450 (1996)。
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通讯作者:
Hiroshi Miyajima et al.: ""Performance Evaluation on High-Performance System-On-Chip Architectures"" IPSJ Technical Report. HPC-62-6. (1996)
Hiroshi Miyajima 等人:““高性能片上系统架构的性能评估””IPSJ 技术报告。
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19
    Research on Design Methodology of Dependable LSI Loading Value and Trust
    • 批准号:
      19200004
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $30.45万
    • 财政年份:
      2007
    • 负责人:
      YASUURA Hiroto
    • 依托单位:
    Development of High-performance Low-power Processor Systems
    • 批准号:
      13023208
    • 项目类别:
      Grant-in-Aid for Scientific Research on Priority Areas
    • 资助金额:
      $40.32万
    • 财政年份:
      2000
    • 负责人:
      YASUURA Hiroto
    • 依托单位:
    The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption
    • 批准号:
      12558029
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $8.51万
    • 财政年份:
      2000
    • 负责人:
      YASUURA Hiroto
    • 依托单位:
    A Study on Delay and Function Test for Core-Based System LSIs
    • 批准号:
      11450143
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $8.45万
    • 财政年份:
      1999
    • 负责人:
      YASUURA Hiroto
    • 依托单位:
    海外基金