Research on Performance Evaluation Technology for High-Performance Computer Systems

高性能计算机系统性能评估技术研究

• 批准号: 07458063
• 负责人: YASUURA Hiroto
• 金额: $ 4.74万
• 依托单位: Kyushu University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1995
• 资助国家: 日本
• 起止时间: 1995 至 1996
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-07458063/
• 关键词: Performance Evaluation; High-Performance Computer Systems; Parallel Computer Systems; System-On-Silicon; Performance Modeling; Performance Estimation; Computer Architecture; VLSI; 並列処理; 計算モデル; オンチップ・マルチプロセッサ; 特殊用途向けプロセッサ; 演繹データベース

The purpose of this research is to develop a comprehensive technology for evaluating the performance, cost, and power consumption of high-performance computer systems. We have performed the following researches in particular.(a) Comprehensive performance evaluation on the compiler and the architecture for high-end microprocessors.(b) Developing and benchmarking the compiler, targetted for application-specific embedded microprocessors, which is enable to optimize the object-code according to the instruction-cache configurations.(c) Developing a modeling methodology for estimating the performance, area cost, and power consumption for "system-on-silicon" class VLSI,and then establishing a platform for evaluating tradeoff among these factors.(d) For parallel computer systems such as workstation-clusters and MPPs (Massively Parallel Processors) ;・Development of performance estimation models,・Study of quantitative evaluation index on scalability, and・Correlation analysis of benchmark programs.

本研究的目的是开发一种综合技术，用于评估高性能计算机系统的性能、成本和功耗。我们特别进行了以下研究。(a)高端微处理器编译器和体系结构的综合性能评估。(b)针对嵌入式微处理器的具体应用，开发了编译器并进行了测试，该编译器能够根据嵌入式微处理器的缓存配置对目标代码进行优化。(c)提出了一种估算“硅上系统”级超大规模集成电路性能、面积成本和功耗的建模方法，并建立了一个评估这些因素之间权衡的平台。(d)针对工作站集群、大规模并行处理器（MPP）等并行计算机系统;·性能评估模型的建立;·可扩展性定量评价指标的研究;·基准程序的相关性分析。

项目成果

H. Tomiyama, H. Yasuura: "Optimal Code Placement of Embedded Software for Instruction Caches" European Design & Test Conference, to appear. (1996)

H. Tomiyama、H. Yasuura：“指令缓存嵌入式软件的最佳代码放置”欧洲设计

Satoko Sakata et al.: ""Performance Evaluation on a Work-station Cluster, TMC CM-5 and Intel Paragon Using a Parallel Homology Analysis Program"" Transactions of IPS Japan. vol.37, no.7. 1440-1450 (1996)

Satoko Sakata 等人：“使用并行同源分析程序对工作站集群、TMC CM-5 和 Intel Paragon 进行性能评估”，IPS Japan 交易。

坂田聡子 他: "ホモロジー解析プログラムを用いたワークステーションクラスタ,TMC CM-5,Intel Paragonの性能評価" 情報処理学会論文誌. 37. 1440-1450 (1996)

Satoko Sakata 等人：“使用同源分析程序对工作站集群、TMC CM-5、Intel Paragon 进行性能评估”日本信息处理学会汇刊 37. 1440-1450 (1996)。

Hiroshi Miyajima et al.: ""Performance Evaluation on High-Performance System-On-Chip Architectures"" IPSJ Technical Report. HPC-62-6. (1996)

Hiroshi Miyajima 等人：““高性能片上系统架构的性能评估””IPSJ 技术报告。

U. Nagashima, S. Sekiguchi, et al.: "An Experience with Super-Linear Speedup Achieved by Parallel Computing on a Workstation Cluster: Parallel Calculation of Density of States of Large Scale Cyclic Polyacenes" Parallel Computing. 21. 1491-1504 (1995)

U. Nagashima、S. Sekiguchi 等人：“工作站集群上并行计算实现超线性加速的体验：大规模循环多并苯态密度的并行计算”并行计算。