HIGH PERFORMANCE DEVICES FOR GIGASCALE INTEGRATED SYSTEMS

适用于千兆级集成系统的高性能设备

• 批准号: 07044111
• 负责人: OHMI Tadahiro
• 金额: $ 3.39万
• 依托单位: TOHOKU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for international Scientific Research
• 财政年份: 1995
• 资助国家: 日本
• 起止时间: 1995 至 1996
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-07044111/
• 关键词: GSI; FOUR-TERMINAL DEVICE; INTELLIGENT ELECTRONIC SYSTEM; LOW POWER; NEURON-MOS; 動きベクトル検出; 重心検出

1. High Functional LSI and Gigascale Integrated System realized by four-terminal deviceWe have realized elemental circuits for an intelligent electronic system by using a four-terminal device, Neuron-MOS (vMOS), as an elemental device. Test circuits were designed, fabricated and evaluated by the measurement of fabricated test circuits.Real-time motion-vector detector and real-time center-of-mass tracer circuit have been developed by using vMOS.High-speed and high-accuracy analog non-volatile memory, vMOS correlator based on Manhattan distance computation, vMOS winner-take-all circuit, which are the key elements of intelligent event-recognition hardware, have been developed. By using the same architecture as the event-recognition hardware, we have developed a vector quantization (VQ) processor chip for real-time motion picture compression using digital circuit technology. The VQ chip exhibits 1,000 times superior speed performance compared to software realization using a microprocessor … More (Pentium 166MHz).2. Low Power Device / Circuit Technology for Gigascale IntegrationLow power operation of the circuit is essential for gigascale integration. We have developed two new low-power circuit schemes for vMOS.One is a sense-amp vMOS logic circuit scheme, which is developed by applying a sense-amplifier to the vMOS logic decision circuit. The other is a deep-threshold vMOS scheme, in which deep threshold transistors and effectively-designed buffer circuit are utilized. Ta-gate SOI-MOSFET which exhibits high performance even with a 1V power supply has been developed. Extremely-low-power adiabatic logic circuit scheme has also been developed for the gigascale integrated circuit.3. Limit to the gigascale integrationOpportunities for gigascale integration are governed by a hierarchy of physical limits whose five levels can be classified as : fundamental, material, device, circuit, and system. This distinctive methodology is extended by elucidating the impact on gigascale integration of random dopant atom placement in the channel region of a MOSFET.4. Optimization of the system configurationBased on a newly derived complete stochastic interconnect distribution, an optimal wiring network architecture is defined that minimizes chip area and power dissipation. Less

1.通过四端器件实现的高性能LSI和千兆级集成系统我们通过使用四端器件Neuron-MOS（vMOS）作为基本器件，实现了智能电子系统的基本电路。通过所制作的测试电路的测量，设计、制作并评估了测试电路。利用vMOS开发了实时运动矢量检测器和实时质心跟踪器电路。高速高精度模拟非易失性存储器、基于曼哈顿距离计算的vMOS相关器、vMOS胜者通吃电路是智能事件识别的关键要素。 硬件等都已开发出来。通过使用与事件识别硬件相同的架构，我们开发了一种矢量量化（VQ）处理器芯片，用于使用数字电路技术进行实时运动图像压缩。与使用微处理器的软件实现相比，VQ 芯片的速度性能高出 1,000 倍……更多（Pentium 166MHz）。2。用于千兆级集成的低功耗器件/电路技术电路的低功耗运行对于千兆级集成至关重要。我们针对vMOS开发了两种新的低功耗电路方案。一种是sense-amp vMOS逻辑电路方案，它是通过将sense-amplifier应用到vMOS逻辑判决电路中而开发的。另一种是深阈值vMOS方案，其中利用深阈值晶体管和有效设计的缓冲电路。开发出即使在 1V 电源下也能发挥高性能的 Ta-gate SOI-MOSFET。针对千兆级集成电路也开发了极低功耗绝热逻辑电路方案。 3．千兆级集成的限制 千兆级集成的机会受到物理限制层次的控制，其五个级别可分为：基础、材料、器件、电路和系统。通过阐明 MOSFET 沟道区域中随机掺杂原子放置对千兆级集成的影响，这种独特的方法得到了扩展。4。系统配置的优化基于新推导的完全随机互连分布，定义了最佳布线网络架构，最大限度地减少了芯片面积和功耗。较少的

项目成果

Hisayuki Shimada and Tadahiro Ohmi: "Current Drive Enhancement by Using High-Permittivity Gate Insulator in SOI MOSFET's and ItsLimitation" IEEE Trans.on Electron Devices. 43. 431-435 (1996)

Hisayuki Shimada 和 Tadahiro Ohmi：“在 SOI MOSFET 中使用高介电常数栅极绝缘体增强电流驱动及其限制”IEEE Trans.on Electron Devices。

T.Shibata: "A Neuron-MOS Neural Network Using Self-Learning-Compatible Synapse Circuits" IEEE J. Solid-State Circuits. 30. 913-922 (1995)

T.Shibata：“使用自学习兼容突触电路的神经元-MOS 神经网络”IEEE J. 固态电路。

T.Shibata: "Advances in Neuron-MOS Applications" Dig. Tech. Papers, 1996 Int. Solid-State Circ. Conf.304-305 (1996)

T.Shibata：“Neuron-MOS 应用的进展”Dig。

T.Ohmi: "Intelligence Implementation on Silicon Based on Four-Terminal Device Electronics" Proc.20th Int.Conf.on Microelectronics. 1. 11-18 (1995)

T.Ohmi：“基于四端子器件电子学的硅智能实现”Proc.20th Int.Conf.on Micro electronics。

T.Ohmi: "Four-Terminal Device Electronics for Intelligent Silicon Integrated System" Ext. Abst., 1995 Int. Conf. on Solid State Devices and Materials. 1-3 (1995)

T.Ohmi：“智能硅集成系统的四端子器件电子学”分机。