Development of ultra-high-speed LSI with gas-isolated-interconnects and Ta metal gate transistors on SOI substrate

SOI基板上气体隔离互连和Ta金属栅极晶体管的超高速LSI的开发

• 批准号: 12305020
• 负责人: OHMI Tadahiro
• 金额: $ 26.62万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (A)
• 财政年份: 2000
• 资助国家: 日本
• 起止时间: 2000 至 2001
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-12305020/
• 关键词: LSI; Ta metal gate; gas-isolated-interconnects; mutual conductance; SOI; interface; trap level; low frequency noise; SOI; BPSG; 無水HF; 銅配線; 金属基板

The purpose of this study is to establish ultra-high speed and high integrated giga scale integration technology that the operating frequency of integrated circuit has been accelerated up to 20 GHz though the maximum speed was so far thought less than 1 GHz in order to develop the ideal device structure, process and material to realize ultra acceleration and low electric power consumption of semiconductor integrated circuit. Because of a problem of Gate depletion, a metal gate should be needed. In this study, Ta metal gate technology characterized by the low-temperature process was developed. Especially, using perfect low-temperature processes below 450 ℃, Ta gate FD-SOI MNSFET using the direct silicon nitride as a gate insulator was made for the first time, and it was found that the sub-threshold coefficient had the ideal property of 66 mV/dec, and the interface property was very good. Furthermore, it is clarified that the mutual conductance of this MNSFET was higher than that of conv … More entional MOSFET at high gate bias region, and also the current drive capability was higher than that of conventional MOSFET.The performance and reliability of the SOI device is strongly influenced to the electric activity defect of Si/SiO_2 (SOI/BOX) interface. In this study, the back gate bias - mutual conductance property of FD-SOI MOSFET was experimentally measured for the first time. Moreover, the formula of the surface potential in the thin film SOI MOS device in consideration of the potential drop between the SOI layer - substrate was newly derived, and also the energy level of the trap level for the SOI/BOX interface corresponding to a kink phenomenon and the high dose SIMOX substrate trap level and its density were clarified.With miniaturization of a MOS device, the electric power-supply voltage must be reduced in order to improve the performance. Therefore, the reduction of the low frequency noise for improving a S/N ratio becomes very important from now on. In this research, it is clarified that the low frequency noise property of a partial depletion type SOI device was analyzed for the first time, and also the noise spectrum in SOI MOSFET adopted the ELTRAN wafer is purely equivalent to 1/f type in the pre-kink domain. Less

本研究的目的是建立超高速、高集成度的千兆级集成技术，使集成电路的工作频率从目前认为的最高速度不到1 GHz提高到20 GHz，从而开发出理想的器件结构、工艺和材料，实现半导体集成电路的超加速和低功耗。由于栅极耗尽的问题，应该需要金属栅极。本研究开发了以低温制程为特征的钽金属闸极技术。特别是首次采用450 ℃以下的低温工艺，制作了直接氮化硅作为栅绝缘层的Ta栅FD-SOI MNSFET，亚阈值系数达到66 mV/dec，界面特性良好。此外，还阐明了这种MNSFET的互导高于常规的MNSFET。 ...更多信息 SOI/BOX（Si/SiO_2）界面的电活性缺陷严重影响SOI器件的性能和可靠性。本文首次对FD-SOI MOSFET的背栅偏压-互导特性进行了实验测量。此外，还导出了考虑SOI层-衬底间电位降的薄膜SOIMOS器件表面电位公式，阐明了对应于扭结现象的SOI/BOX界面陷阱能级和高剂量SIMOX衬底陷阱能级及其密度，随着MOS器件的小型化，必须降低电源电压以提高性能。在本研究中，首次对部分耗尽型SOI器件的低频噪声特性进行了分析，并阐明了采用ELTRAN晶片的SOI MOSFET的噪声谱在预扭折域中完全等效于1/f型。少

项目成果

Takeo Ushiki: "Chemical Reaction Concerns of Gate Metal with Gate Dielectric in Ta Gate MOS Devices"IEEE Transactions on Electron Devices. 47・11. 2201-2207 (2000)

Takeo Ushiki：“Ta 栅极 MOS 器件中栅极金属与栅极电介质的化学反应问题”IEEE Transactions on Electron Devices 47・11 2201-2207 (2000)。

Akihiro Morimoto: "Interconnect and Substrate Structure for Gigascale Integration"Jpn. J. Appl. Phys. Vol.40・1, No.4B. (2001)

森本明宏：“千兆级集成的互连和基板结构”J.Appl.Vol.40・1，No.4B。

Takeo Ushiki: "Effect of Starting SOI Material Quality on Low-Frequency Noise Characteristics in Partially Depleted Floating-Body SOI MOSFETs"IEEE Electron Device Letters. 21・12. 610-612 (2000)

Takeo Ushiki：“启动 SOI 材料质量对部分耗尽浮体 SOI MOSFET 低频噪声特性的影响”IEEE 电子器件快报 21・12 (2000)。

Akihiro Morimoto: "Interconnect and Substrate Structure for Gigascale Integration"Jpan. J. Appl. Phys.. 40・1・4B. 3038-3043 (2001)

Akihiro Morimoto：“千兆级集成的互连和基板结构”日本。 Phys. 40・1・4B 3038-3043（2001）

Yuji Saito: "Improvement of MOSFET Subthreshold Leakage Current by its Irradiation with Hydrogen Radicals Generated in Microwave-Excited High-Density Inert Gas Plasma"2001 IEEE international reliability physics symposium. 47・11. 319-326 (2001)

Yuji Saito：“通过微波激发高密度惰性气体等离子体中产生的氢自由基来改善 MOSFET 亚阈值漏电流”2001 IEEE 国际可靠性物理研讨会 47・11。