Rapid Prototyping Technology for Large Scale Logic Circuits

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As mentioned in the research plan, we study Rapid Prototyping Technology for Large Scale Logic Circuits. The followings are major results of the research.1. We developed interactive logic partitioning method which divides gate level netlist into FPGAs utilizing knowledge of designer. This method enables effective logic partitioning independent of design entries such as schematic capture and hardware description language. Utilization ratio and operation speed of FPGA are improved.2. In addition to method I., two automatic logic partitioning methods were introduced into rapid prototyping environment, which divide logic circuits from gate level netlist and hardware description language. Combining three partitioning methods provided more efficient prototyping environment.3. We applied the rapid prototyping environment to VLSI system design education. Adopting Graphical HDL entry tool, design specifications of developing system were immediately utilized design entry. It provided not only effective design methods but also design tool for novice designers.4. We applied the rapid prototyping environment to image processing LSI design for multimedia equipment. This results show that it provided easily to investigation a suitable architecture for operation speed and circuit size using LPGA.