Development of Self-Repair Dependable system on FPGA

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SRAM-based field programmable gate arrays (FPGAs) are vulnerableto a soft-errors and physical hard-errors. In order to overcome this issues, our goalis the development of self-repair dependable system on FPGA using following three factors.First, we propose the Triple Modular Redundancy (TMR) scheme coupled with the dynamicpartial reconfiguraition to remove SEU from the FPGA’s configuration memory. Second,we propose an evaluation method that provides results in terms of the realistic failurein time (FIT) by using reconfiguration-based fault-injection analysis. By using theproposed method, we successfully evaluated a TMR circuit and could discuss the resultin terms of realistic FIT data. Finally, a uniforming design technique for PRRs(PartialReconfigurable Regions) are introduced in order to relocate their PRB(PartialReconfigurable Block). Additionally, our design technique enables to implement largepartial module by combining neighboring PRRs.