Development of Self-Repair Dependable system on FPGA

基于SRAM的现场可编程门阵列（FPGA）具有软错误和物理硬错误兼容性。为了克服这些问题，我们的目标是在FPGA上开发自修复可靠系统，主要从以下三个方面进行：首先，我们提出了三重模块冗余（TMR）方案，结合动态部分重构技术，从FPGA的配置存储器中去除SEU。其次，我们提出了一种评估方法，提供的实际故障时间（FIT）方面的结果，通过使用基于重构的故障注入分析。通过使用所提出的方法，我们成功地评估了一个TMR电路，并可以讨论的结果条款的现实FIT数据。最后，为了实现部分可重构块的重定位，提出了一种部分可重构区域的统一设计方法。此外，我们的设计技术，使实现largepartial模块结合相邻的PRR。

SRAM-based field programmable gate arrays (FPGAs) are vulnerableto a soft-errors and physical hard-errors. In order to overcome this issues, our goalis the development of self-repair dependable system on FPGA using following three factors.First, we propose the Triple Modular Redundancy (TMR) scheme coupled with the dynamicpartial reconfiguraition to remove SEU from the FPGA’s configuration memory. Second,we propose an evaluation method that provides results in terms of the realistic failurein time (FIT) by using reconfiguration-based fault-injection analysis. By using theproposed method, we successfully evaluated a TMR circuit and could discuss the resultin terms of realistic FIT data. Finally, a uniforming design technique for PRRs(PartialReconfigurable Regions) are introduced in order to relocate their PRB(PartialReconfigurable Block). Additionally, our design technique enables to implement largepartial module by combining neighboring PRRs.