Study on Interconnection Networks Towards Realization of a Reconfigurable Parallel Computer

实现可重构并行计算机的互连网络研究

基本信息

批准号：
05680278
负责人：
SUEYOSHI Toshinori
金额：
$ 1.28万
依托单位：
Kyushu Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (C)
财政年份：
1993
资助国家：
日本
起止时间：
1993 至 1994
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-05680278/
关键词：
Parallel computer Interconnection network Reconfigurable FPGA Processor array Hard macro

项目摘要

The following describe the results on the study of interconnection networks towards realization of a reconfigurable parallel computer which were achieved in accordance with the research project plan :1.On the interconnection network of reconfigurable MIMD parallel computer, the points to realize diverse topologies were summarized and the configuration method of a reconfigurable interconnection network which can directly realize the desired topology were clarified.2.Furthermore, the concept of reconfigurable SIMD parallel computer which can flexibly rearrange not only its interconnection network but also its processor array elements to adapt with the application were described. Likewise, its configuration method and fault tolerance ability were confirmed.3.The mapping strategies to realize the desired reconfigurable parallel computer utilizing FPGA,were clarified. Moreover, we fonud out that the generation time has an adverse effect on the automatic generation of FPGA configuration data … More based on mapping algorithm. Consequently, we prepared a library of FPGA configuration data to reduce the time to reconfigure topologies.4.In the process of preparing the above library, the problem of reducing the operation speed in high density implementation caused by wire delay which is dependent on the placement and routing procedures, and the difficulty of control have occurred. So, the idea to control the fluctuation of wire delay was necessary. Thus, a new high performance and high density implementation method was developed to support the preparation of the hard macro of several circuits which cannot be handled by commercial tools.5.A prototype of reconfigurable SIMD parallel computer was developed and had proven to realize processor arrays of different architectures. Furthermore, it was confirmed that high density and high performance implementation can be achieved utilizing the above-mentioned method compared with commercial CAE tools. With these, an integrated development support environment was constructed to develop the potentials of reconfigurable parallel computers. Less

以下描述了互连网络研究实现可重新配置的平行计算机的结果的结果，该计算机是根据研究项目计划实现的：1。在可重新配置的MIMD平行计算机的互连网络中，概述了潜水拓扑的点，可以概括了desconnection网络的构造方法。可重新配置的可重新配置SIMD并行计算机，它不仅可以灵活地重新排列其互连网络，还可以描述其以适应应用程序的处理器数组元素。同样，确认了其配置方法和容错能力。3。阐明了使用FPGA实现所需重新配置的平行计算机的映射策略。此外，我们发现，生成时间对FPGA配置数据的自动生成产生不利影响……更多基于映射算法。因此，我们准备了一个FPGA配置数据库，以减少重新配置拓扑的时间。4。在准备上述库的过程中，降低由电线延迟引起的高密度实现的操作速度的问题，这取决于位置和路由过程，并且发生了难度。因此，需要控制电线延迟波动的想法。这是开发了一种新的高性能和高密度实现方法，以支持无法通过商业工具无法处理的几个电路的硬宏的制备。5。开发了可重构的SIMD平行计算机的原型，并已证明可以实现不同建筑的处理器阵列。此外，已经证实，与商业CAE工具相比，可以使用上述方法实现高密度和高性能实现。通过这些，建立了一个集成的开发支持环境，以开发可重构平行计算机的潜力。较少的