Study on the Speed-Up of Communications Protocol Processing by Parallel Processing
Study on the Speed-Up of Communications Protocol Processing by Parallel Processing
批准号:
01460256
负责人:
SUEYOSHI Toshinori
金额:
$3.33万
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (B)
财政年份:
1989
资助国家:
日本
项目状态:
已结题
起止时间:
1989 至 1990
中文摘要
根据研究实施计划,研究设计一种协议机,通过基于标准协议即TCP/IP协议的并行处理来加速通信协议的处理,以加快网络的有效传输速率。本研究的主要成果如下:通信协议处理模型及并行性提取:基于标准协议中的层次和虚拟概念,可以在按层次顺序排列的层内实现并行性,并通过并行处理实现加速。通信协议处理的动态分析:动态分析表明,在通信协议处理中,传输处理所需的时间非常重要,层与层之间的数据复制过程负担很大。此外,要提高有效传输速率,仅仅加快通信协议本身的处理速度是不够的,而且通信控制也是必不可少的。协议机体系结构的研究:考虑到按层次顺序排列的层之间可以应用的并行性,将空间并行处理和时效性并行处理相结合,构成了协议机的基本体系结构。针对通信控制的提速问题,指出了确认信号(ACK)的延迟是提速的主要原因,并提出了TCP/IP框架下的提速实现技术。原型协议机的开发:根据3中描述的协议机。,为加快数据复制过程,可采用专用硬件和新型互连网络。原型性能评估:通过协议处理时间与传输效率的关系,证实了加快协议处理速度对提高有效传输速率有显著效果。特别是,随着高速网络的不断搜索和扩散,加快协议的处理速度将变得更加重要。少
英文摘要
According to the research implementation plan, the research was conducted to devise a protocol machine to accelerate the communication protocols processing by parallel processing based on standard protocols, i.e., the TCP/IP protocols, with the goal of speeding up the network effective transmission rate. The following describes the major results of this research :1. Communication protocols processing model and parallelism extraction :Parallelism can be applied within the layers which are arranged in hierarchical order based on the hierarchy and virtual concepts in standard protocols, and acceleration can be attained through parallel processing.2. Dynamic analysis of communication protocols processing :Dynamic analysis shows that the time needed for transmission processing in communication protocols processing is essential, and the data copy process between layers is a heavy load. Moreover, to speed up the effective transmission rate, this cannot be attained by just accelerating the com … More munications protocols processing itself but also the communication controls which are likewise indispensable.3. Research of protocol machine architecture :Taking into account the parallelism which can be applied within the layers which are arranged in the hierarchical order, and the combination of the spatial and timely parallel processing constitutes the basic architecture of the protocol machine. Furthermore, with regards to speeding up by communication control, it was pointed out that the delay of the acknowledgment signal (ACK) is the primary cause, and the speed up implementation techniques within the framework of the TCP/IP methodology are proposed.4. Development of prototype protocol machine :In accordance with the protocol machine described in 3., to speed up the data copy process is by implemention to a dedicated hardware and using new type of interconnection network.5. Performance evaluation for the prototype :The relationship between the protocols processing time and transmission efficiency confirmed that speeding up the protocols processing will have a significant effect in improving the effective transmission rate. In particular, with the continuing search and proliferation of high speed networks, it will be indeed much more important to speed up the protocols processing. Less
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Bernady Apduhan: "An Investigation on the Speedーup of Communications Protocol Processing" Proc.of the 5th International joint Workshop on Computer Communications. 1-10 (1990)
Bernady Apduhan:第五届国际计算机通信联合研讨会“通信协议处理加速的调查”(1990)。
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末吉 敏則: "書換え可能なLSIによる可変構造型相互結合網の実現法" 情報処理学会「並列処理シンポジウム JSPP'91」論文集. (1991)
Toshinori Sueyoshi:“使用可重写LSI实现可变结构互连网络的方法”日本信息处理学会“并行处理研讨会JSPP91”论文集(1991)。
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Akira Fukuda, Yuuji Fukuzawa, Yoshiaki Hirotani, Kazuaki Murakami, Toshinori Sueyoshi and Shinji Tomita: "A Parallel/Distributed Operating System for the Reconfigurable Parallel Processor" IPSJ SIG Reports on OperatingSystems. OS43. 1-8 (1989)
Akira Fukuda、Yuuji Fukuzawa、Yoshiaki Hirotani、Kazuaki Murakami、Toshinori Sueyoshi 和 Shinji Tomita:“用于可重新配置并行处理器的并行/分布式操作系统”IPSJ SIG 关于操作系统的报告。
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Toshinori Sueyoshi, Kouhei Hano and Itsujiro Arita: "An Approach to Realizing a Reconfigurable Interconnection Network Using Field Programmable Gate Arrays" Proc. of the IPSJ Joint Symposium on Parallel Processing. (1991)
Toshinori Sueyoshi、Kouhei Hano 和 Itsujiro Arita:“使用现场可编程门阵列实现可重构互连网络的方法”Proc。
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末吉 敏則: "新しい可変構造型相互結合網の提案" 情報処理学会研究報告. ARC85. 79-86 (1990)
Toshinori Sueyoshi:“新的可变结构互连网络的提议”日本信息处理学会ARC85(1990)。
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共 15 条
Development of Self-Repair Dependable system on FPGA
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批准号:22300018
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$11.81万
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财政年份:2010
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负责人:SUEYOSHI Toshinori
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依托单位:
Research for Reconfigurable System Technology using Fine Grained Cell Architecture
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批准号:17300021
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$10.08万
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财政年份:2005
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负责人:SUEYOSHI Toshinori
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依托单位:
Research and Development of Flexible Hardware and Remote Reconfiguration Techniques
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批准号:14390041
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$7.04万
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财政年份:2002
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负责人:SUEYOSHI Toshinori
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依托单位:
Study on Next Generation FPGA toward Reconfigurable Computing
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批准号:11490028
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$9.41万
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财政年份:1999
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负责人:SUEYOSHI Toshinori
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依托单位:
Study of Reconfigurable Processor using Programmable LSI
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批准号:09680344
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.05万
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财政年份:1997
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负责人:SUEYOSHI Toshinori
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依托单位:
Rapid Prototyping Technology for Large Scale Logic Circuits
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批准号:09559014
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$8.32万
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财政年份:1997
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负责人:SUEYOSHI Toshinori
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依托单位:
Study of Cluster Computing on a High Speed Network Environment
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批准号:07680365
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$1.47万
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财政年份:1995
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负责人:SUEYOSHI Toshinori
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依托单位:
Study on Interconnection Networks Towards Realization of a Reconfigurable Parallel Computer
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批准号:05680278
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项目类别:Grant-in-Aid for General Scientific Research (C)
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资助金额:$1.28万
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财政年份:1993
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负责人:SUEYOSHI Toshinori
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依托单位:
海外基金