Research for Reconfigurable System Technology using Fine Grained Cell Architecture

本研究根据研究目的及研究计画，取得以下研究成果。可重构逻辑IPVGLC（Variable Grain Logic Cell）是针对可重构系统提出的可重构器件体系结构。它具有新奇的可变晶粒结构，统一了细晶粒和粗晶粒的结构。我们评估VGLC架构与传统的FPGA相比，使用相同的FPGA的布线资源，使用手动映射的算术电路。评估结果表明，VGLC的布局面积最小相比，传统的FPGA集群晶体管级优化。计算结果还表明，AT积也最小化了约66%.动态可重构系统的实时操作系统增强和逻辑虚拟化研究我们研究了动态可重构系统的实时操作系统增强和逻辑虚拟化机制。这些机制支持在不停止整个系统的处理的情况下保持执行，任务调度包括重新配置任务。评估结果表明，该机制支持嵌入式处理器的自重构和网络环境下的透明功能执行，具有较高的实用性和有效性.可重构系统设计工具的研究我们研究了面向部分重构的可重构系统设计工具，它通过提取应用电路中的共享功能来支持有效的重构。评估结果表明，JPEG解码器和MPEG-2解码器的共享电路实现，重构时间减少了约60%。在此基础上，研究了共享电路自动提取的设计方法。结果表明，在特定的目标应用中，查找表减少了约4%，寄存器减少了约23%，逻辑块减少了约9%。

The following research results are obtained in according to "Purpose of the research" and "Research plan".1. The Research for Reconfigurable Logic IPVGLC(Variable Grain Logic Cell)is proposed reconfigurable device architecture for reconfigurable system. It has novelty in the variable grain structure unified fine grain and coarse grain architecture. We evaluate VGLC architecture with same routing resource of FPGA compared with conventional FPGA using manually mapped arithmetic circuit. The evaluation result shows that layout area of VGLC is minimized compared with conventional FPGA cluster with transistor level optimization. Also the result shows that the AT product is also minimized about 66%.2. The Research of RTOS Enhancement and Logic Virtualization for Dynamically Reconfigurable SystemWe develop the mechanisms of RTOS enhancement and logic virtualization for dynamically reconfigurable system. These mechanisms support to keep executing without stopping the processing of the entire system with the task schedule including the reconfiguration task. The evaluation results show that the reconfigurable system using the mechanism is high practicality and effectively, because the mechanisms support self-reconfiguration with embedded processor and transparent function execution via network environment.3. The Research of Design Tools for Reconfigurable SystemWe research the design tools of reconfigurable system for partial-reconfiguration, which supports effective reconfiguration with extracted shared function in the application circuits. The evaluation result shows the reconfiguration time is reduced about 60% with the shared circuit's implementation of JPEG decoder and MPEG-2 decoder. Furthermore, the design method for automatic extraction of shared circuits is studied. The result shows that the LUTs are reduced about 4%, registers are reduced about 23% and logic blocks are reduced about 9% in certain target application.