Research for Reconfigurable System Technology using Fine Grained Cell Architecture

根据“研究目的”和“研究计划”，得出以下研究结果。针对可重构系统，提出了可变粒度逻辑单元（IPVGLC）的可重构器件体系结构。它在细晶粒和粗晶粒统一的变晶粒结构方面具有新颖性。在FPGA路由资源相同的情况下，对VGLC架构与传统FPGA采用手工映射的算法电路进行了比较。评估结果表明，通过晶体管级优化，与传统FPGA集群相比，VGLC的布局面积最小。结果表明，AT产物也减少了约66%。动态可重构系统的RTOS增强与逻辑虚拟化研究开发了动态可重构系统的RTOS增强与逻辑虚拟化机制。这些机制支持在不停止整个系统的任务调度（包括重新配置任务）的情况下继续执行。评价结果表明，基于该机制的可重构系统具有较高的实用性和有效性，因为该机制支持嵌入式处理器的自重构和通过网络环境透明的功能执行。可重构系统设计工具的研究研究了可重构系统的部分重构设计工具，该工具支持在应用电路中提取共享功能进行有效重构。评估结果表明，共享电路实现JPEG解码器和MPEG-2解码器后，重构时间减少约60%。在此基础上，研究了共享电路自动提取的设计方法。结果表明，在特定的目标应用中，lut减少了约4%，寄存器减少了约23%，逻辑块减少了约9%。

The following research results are obtained in according to "Purpose of the research" and "Research plan".1. The Research for Reconfigurable Logic IPVGLC(Variable Grain Logic Cell)is proposed reconfigurable device architecture for reconfigurable system. It has novelty in the variable grain structure unified fine grain and coarse grain architecture. We evaluate VGLC architecture with same routing resource of FPGA compared with conventional FPGA using manually mapped arithmetic circuit. The evaluation result shows that layout area of VGLC is minimized compared with conventional FPGA cluster with transistor level optimization. Also the result shows that the AT product is also minimized about 66%.2. The Research of RTOS Enhancement and Logic Virtualization for Dynamically Reconfigurable SystemWe develop the mechanisms of RTOS enhancement and logic virtualization for dynamically reconfigurable system. These mechanisms support to keep executing without stopping the processing of the entire system with the task schedule including the reconfiguration task. The evaluation results show that the reconfigurable system using the mechanism is high practicality and effectively, because the mechanisms support self-reconfiguration with embedded processor and transparent function execution via network environment.3. The Research of Design Tools for Reconfigurable SystemWe research the design tools of reconfigurable system for partial-reconfiguration, which supports effective reconfiguration with extracted shared function in the application circuits. The evaluation result shows the reconfiguration time is reduced about 60% with the shared circuit's implementation of JPEG decoder and MPEG-2 decoder. Furthermore, the design method for automatic extraction of shared circuits is studied. The result shows that the LUTs are reduced about 4%, registers are reduced about 23% and logic blocks are reduced about 9% in certain target application.