Research for Reconfigurable System Technology using Fine Grained Cell Architecture

使用细粒度单元架构的可重构系统技术研究

基本信息

批准号：
17300021
负责人：
SUEYOSHI Toshinori
金额：
$ 10.08万
依托单位：
Kumamoto University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2005
资助国家：
日本
起止时间：
2005 至 2007
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-17300021/
关键词：
Reconfigurable System Fine Grained Cell System LSI FPGA Real Time OS

项目摘要

The following research results are obtained in according to "Purpose of the research" and "Research plan".1. The Research for Reconfigurable Logic IPVGLC(Variable Grain Logic Cell)is proposed reconfigurable device architecture for reconfigurable system. It has novelty in the variable grain structure unified fine grain and coarse grain architecture. We evaluate VGLC architecture with same routing resource of FPGA compared with conventional FPGA using manually mapped arithmetic circuit. The evaluation result shows that layout area of VGLC is minimized compared with conventional FPGA cluster with transistor level optimization. Also the result shows that the AT product is also minimized about 66%.2. The Research of RTOS Enhancement and Logic Virtualization for Dynamically Reconfigurable SystemWe develop the mechanisms of RTOS enhancement and logic virtualization for dynamically reconfigurable system. These mechanisms support to keep executing without stopping the processing of the entire system with the task schedule including the reconfiguration task. The evaluation results show that the reconfigurable system using the mechanism is high practicality and effectively, because the mechanisms support self-reconfiguration with embedded processor and transparent function execution via network environment.3. The Research of Design Tools for Reconfigurable SystemWe research the design tools of reconfigurable system for partial-reconfiguration, which supports effective reconfiguration with extracted shared function in the application circuits. The evaluation result shows the reconfiguration time is reduced about 60% with the shared circuit's implementation of JPEG decoder and MPEG-2 decoder. Furthermore, the design method for automatic extraction of shared circuits is studied. The result shows that the LUTs are reduced about 4%, registers are reduced about 23% and logic blocks are reduced about 9% in certain target application.

根据“研究目的”和“研究计划”。1。可重构逻辑IPVGLC（可变晶粒逻辑单元）的研究是针对可重构系统的可重构设备体系结构的。它在可变谷物结构统一细晶粒和粗粒结构中具有新颖性。我们使用手动映射的算术电路评估了具有FPGA相同的FPGA路由资源的VGLC架构。评估结果表明，与传统的FPGA群集相比，VGLC的布局面积最小化，并具有晶体管水平优化。结果还表明，AT产品也被最小化了约66％.2。 RTOS增强和逻辑虚拟化的研究为动态重新配置Systemwe开发了RTOS增强和逻辑虚拟化的机制，以动态可重新配置系统。这些机制支持继续执行，而无需停止使用任务计划（包括重新配置任务）的整个系统处理。评估结果表明，使用该机制的可重构系统具有很高的实用性，并且有效，因为该机制通过嵌入式处理器和通过网络环境进行透明功能执行的机制支持自我调控。3。可重新配置Systemwe的设计工具的研究研究了针对部分重新配置的可重新配置系统的设计工具，该工具支持在应用电路中使用提取的共享功能的有效重新配置。评估结果表明，随着共享电路的JPEG解码器和MPEG-2解码器的实现，重新配置时间减少了约60％。此外，研究了自动提取共享电路的设计方法。结果表明，LUTS减少了约4％，在某些目标应用中减少了约23％的寄存器，逻辑块减少了约9％。

项目成果

期刊论文数量（0）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Applying the small-world network to routing structure of FPGAs

DOI：
10.1109/fpl.2005.1515700
发表时间：
2005-10
期刊：
International Conference on Field Programmable Logic and Applications, 2005.
影响因子：
0
作者：
Hisashi Tsukiashi;M. Iida;T. Sueyoshi
通讯作者：
Hisashi Tsukiashi;M. Iida;T. Sueyoshi

粒度可変構造を持つ再構成論理セルを用いた基本演算回路の実装

使用可变粒度结构的可重构逻辑单元实现基本算术电路