Study of Reconfigurable Processor using Programmable LSI

利用可编程LSI的可重构处理器的研究

基本信息

批准号：
09680344
负责人：
SUEYOSHI Toshinori
金额：
$ 2.05万
依托单位：
Kumamoto University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1998
项目状态：
已结题

项目摘要

As mentioned in the research plan, we study Reconfigurable Processor using Reconfigurable LSI.The followings are major results of the research.1. A system prototype of on-chip multiprocessor using system-on-silicon technology was considered as a part of basic research for reconfigurable processor. The system employed the reconfigurability that is a feature of reconfigurable processor and the speed up by hardware implementation. The reconfiguration feature was adapted to hardware with thread control mechanism and its architecture was described. A reconfigurable logic with the dynamic reconfiguration feature which can ignore its overhead of reconfiguration enables that the processor execute both the processor synchronization and the thread scheduling in parallel, and high performance was achieved.2. Java was selected as a programming language to write applications and it stands for a part of program development environment for reconfigurable processor. Java is suited for writing parallel applications because it supports concurrent programming in its language specification. A prototype program that translates from Java to hardware description language was developed and this translator was realized with consideration for not only simulation but also implementation into FPGAs.3. We applied the reconfigurable processor to three applications ; Fast Fourier Transform (FFT), N Queens problem, and LAN simulator. Evaluation results showed advantages about 180 times speed up comparison with conventional workstation in applications including highly parallelism. Also, 10 times speed up was recognized in applications restricted parallelism with hardware resource limitation.

如研究计划中所述，我们使用可重构LSI研究可重构处理器。以下是研究的主要结果。1。使用System-Silicon技术的芯片多处理器的系统原型被视为可重构处理器基础研究的一部分。该系统采用了可重构性，这是可重新配置处理器的功能以及硬件实现的速度。重新配置功能通过线程控制机制适应了硬件，并描述了其体系结构。具有动态重新配置功能的可重构逻辑，可以忽略其重新配置的开销，使处理器可以并行执行处理器同步和线程调度，并实现了高性能。2。 Java被选为编程语言来编写应用程序，它代表了可重构处理器程序开发环境的一部分。 Java适合编写并行应用程序，因为它支持其语言规范中的并发编程。从Java转换为硬件描述语言的原型程序已开发出来，并且该翻译人员不仅考虑了模拟，而且还考虑到FPGA.3。我们将可重构处理器应用于三个应用程序；快速傅立叶变换（FFT），N Queens问题和LAN模拟器。评估结果显示，在包括高度并行性在内的应用中，与常规工作站相比，优势与常规工作站进行比较约180倍。同样，在限制了硬件资源限制的应用程序中，确认了10倍的速度。