Design of Electronic Properties and Development of High-Mobility Channel Technology for Low Power/High-Speed Nano-CMOS Devices

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We have investigated the crystal growth and electronic properties of strained Ge and GeSn epitaxial layers for realizing low power and high speed CMOS devices. We achieved the growth of very high Sn content GeSn growth and the reduction of defect density in GeSn epitaxial layers by substrate design, low temperature growth, and strain engineering. We also developed engineering technology of point defects, carrier properties, and MOS interface for GeSn materials. In addition, we demonstrated the fabrication of GOI and SGOI wafers and the improvement on the carrier mobility in those layers.