Heralded single-photon source with on-chip heralding detector

单光子之间的量子干涉是光量子计算的先决条件。这一要求意味着我们需要明亮的、确定性的单光子源，它能够持续地产生单光子，同时在单一模式下是纯的和不可区分的。[1,2]光子集成电路（PIC）技术允许我们设计非线性单光子对源，以同时满足所有这些要求，但它们仍然具有固有的概率性。尽管如此，这种源的预示性质允许我们将它们的数组复用以获得更确定的逻辑源[1,3]。然而，多路复用需要通过电子设备进行前馈，与光子的速度相比，电子设备的前馈速度较慢，需要我们使用较长的光延迟线，以便将预示信号及时转换为预示光子的开关控制信号。较长的延迟线是不受欢迎的，因为它越长，其中损失的光子越多，因此亮度就越低。减少前馈时间延迟长度的第一步，即减少延迟线长度的第一步，是将预警光子的探测器尽可能靠近源，或者，对于基于pic的光子源，在同一芯片上。这是绝对不可避免的，特别是如果最终目标是一个完全集成的片上多路复用。此外，将预告探测器集成在芯片上还可以提高系统预告事件的概率，因为它可以消除源和探测器之间传输相关损耗的潜在来源，例如芯片到光纤耦合器的损耗、光纤损耗等。一般来说，单光子可以通过多种方式检测，但唯一可以同时实现高效率、低暗计数率、低复位时间、低功耗和低功耗的方法。低抖动是通过超导纳米线单光子探测器（SNSPD）实现的，唯一的代价是必须在低温下操作[3,4]。在我们的案例中，单光子源的多路复用，然而，需要所有上述的性能[1]，使它成为我们唯一的选择。在这个博士学位的第一年，我将尝试将snspd直接集成在波导上，使其接近上述动机的源，目的是只有低到中等的性能。系统预告事件概率的提升也要求预告光子的滤波器产生最小的损失。此外，为了防止影响预告效率的虚假预告（给定预告事件交付预告单光子的概率），它还需要保持高消光比，以抑制可能存在于芯片中的泵浦噪声和不必要的非线性过程[3,5]。基于文献中现有解决方案并与内部制造的snspd共同开发的一系列过滤策略和设计的开发将是第二年的重点。如果一切按计划进行，在第3年，将使用前几年的组件设计、制造和后处理带有片上预告探测器的单光子源的最终PIC，并且有望展示片上预告。

Quantum interference between single-photons is a prerequisite of an optical quantum computing. This requirement means that we requires bright, deterministic single-photon sources that can consistently produce single-photons which are simultaneously pure and indistinguishable into a single mode. [1,2] Photonic integrated circuit (PIC) technology allows us to engineer nonlinear single-photon pair sources to satisfy all these requirements simultaneously except that they are still inherently probabilistic. Nevertheless, the heralded nature of such sources allows us to multiplex an array of them to achieve a more deterministic logical source [1,3]. Multiplexing, however, requires feedforwarding via electronics which is slow compared to the speed of photons, requiring us to use a long optical delay line, so that the heralding signal can be transduced to a switch controlling signal for the heralded photon in time. The long delay line is undesirable as the longer it is, the more photons are loss in it, and hence less brightness. The first step towards reducing the length of the feedforwarding time delay, and thus the delay line, is to place the detector for the heralding photon as close as possible to the source, or, for PIC-based photon source, on the same chip. This is absolutely unavoidable especially if the end goal is a fully integrated on-chip multiplexing. Furthermore, integrating the heralding detector on-chip would also boost the system heralding event probability as it would eliminate potential sources of the transmission-related loss between the source and the detector, e.g., chip-to-fibre coupler loss, fibre loss, etc.Single-photons in general may be detected by many means but the only mean that can simultaneously achieve high efficiency, low dark count rate, low reset time, and low jitter is via superconducting nanowire single-photon detectors (SNSPD) with the only expense of having to operate it at cryogenic temperature [3,4]. In our case, the heralding of single-photon source for multiplexing, however, requires all the aforementioned performances [1], making it our only choice. In year 1 of this PhD, I will attempt to integrate SNSPDs directly on top of waveguides, allowing it to be close to the source as motivated above, with the aim of only low-to-moderate performances. The promise of the boost in the system heralding event probability also requires that the filter for the heralding photon incur minimal loss. In addition, to prevent false heralding which will impact the heralding efficiency (the probability of delivering a heralded single-photon given a heralding event), it also needs to maintain the high extinction ratio necessary to reject the noises from the pump and the unwanted non-linear processes [3,5] that may be present in the chip. The development of a range of filtering strategies and designs-based on existing solutions in literature and developed jointly with the SNSPDs fabricated in-house-will be the focus of year 2. If everything goes according to plan, in year 3, the final PIC for a single-photon source with on-chip heralding detector may be designed, fabricated and post-processed, using the components from the previous years, and hopefully, the on-chip heralding will be demonstrated.