Heralded single-photon source with on-chip heralding detector

单光子间的量子干涉是光量子计算的前提。这一要求意味着我们需要明亮的、确定的单光子源，能够始终如一地产生同时纯净且无法区分为单模的单光子。[1，2]光子集成电路(PIC)技术允许我们设计非线性单光子对源，以同时满足所有这些要求，除非它们仍然是固有的概率。然而，这种源的预知性质允许我们多路传输它们的阵列，以实现更具确定性的逻辑源[1，3]。然而，多路复用需要通过电子学进行前馈，这与光子的速度相比是很慢的，这就要求我们使用一条很长的光学延迟线，以便预警信号可以及时转换为预警光子的开关控制信号。长延迟线是不受欢迎的，因为它越长，其中损失的光子就越多，因此亮度就越低。减少前馈时延的长度以及延迟线的第一步是将用于预告光子的探测器尽可能靠近源，或者对于基于PIC的光子源，将其放置在同一芯片上。这是绝对不可避免的，特别是如果最终目标是完全集成的片上多路复用器。此外，将预警探测器集成在芯片上也将提高系统预警事件的概率，因为它将消除源和探测器之间与传输相关的损耗的潜在来源，例如，芯片到光纤耦合器损耗、光纤损耗等。通常，单光子可以通过许多方法来检测，但是能够同时实现高效率、低暗计数率、低重置时间和低抖动的唯一手段是通过超导纳米线单光子探测器(SNSPD)，唯一的代价是必须在低温下操作它[3，4]。然而，在我们的情况下，单光子源用于多路复用需要所有上述性能[1]，这使它成为我们唯一的选择。在本博士学位的第一年，我将尝试将SNSPD直接集成到波导的顶部，使其能够像上面所述那样靠近源，目标是只实现低到中等的性能。为了在系统中提高预警事件的概率，还要求预警光子的滤光片造成的损失最小。此外，为了防止将影响预警效率的错误预警(在给定预警事件的情况下传递被预警的单光子的概率)，它还需要保持必要的高消光比，以抑制来自泵浦的噪声和芯片中可能存在的不需要的非线性过程[3，5]。基于文献中现有解决方案并与内部制造的SNSPD联合开发的一系列过滤策略和设计将是第二年的重点。如果一切按计划进行，在第三年，具有片上告警探测器的单光子源的最终PIC可能会设计、制造和后处理，使用前几年的组件，希望芯片上的告警将得到演示。

Quantum interference between single-photons is a prerequisite of an optical quantum computing. This requirement means that we requires bright, deterministic single-photon sources that can consistently produce single-photons which are simultaneously pure and indistinguishable into a single mode. [1,2] Photonic integrated circuit (PIC) technology allows us to engineer nonlinear single-photon pair sources to satisfy all these requirements simultaneously except that they are still inherently probabilistic. Nevertheless, the heralded nature of such sources allows us to multiplex an array of them to achieve a more deterministic logical source [1,3]. Multiplexing, however, requires feedforwarding via electronics which is slow compared to the speed of photons, requiring us to use a long optical delay line, so that the heralding signal can be transduced to a switch controlling signal for the heralded photon in time. The long delay line is undesirable as the longer it is, the more photons are loss in it, and hence less brightness. The first step towards reducing the length of the feedforwarding time delay, and thus the delay line, is to place the detector for the heralding photon as close as possible to the source, or, for PIC-based photon source, on the same chip. This is absolutely unavoidable especially if the end goal is a fully integrated on-chip multiplexing. Furthermore, integrating the heralding detector on-chip would also boost the system heralding event probability as it would eliminate potential sources of the transmission-related loss between the source and the detector, e.g., chip-to-fibre coupler loss, fibre loss, etc.Single-photons in general may be detected by many means but the only mean that can simultaneously achieve high efficiency, low dark count rate, low reset time, and low jitter is via superconducting nanowire single-photon detectors (SNSPD) with the only expense of having to operate it at cryogenic temperature [3,4]. In our case, the heralding of single-photon source for multiplexing, however, requires all the aforementioned performances [1], making it our only choice. In year 1 of this PhD, I will attempt to integrate SNSPDs directly on top of waveguides, allowing it to be close to the source as motivated above, with the aim of only low-to-moderate performances. The promise of the boost in the system heralding event probability also requires that the filter for the heralding photon incur minimal loss. In addition, to prevent false heralding which will impact the heralding efficiency (the probability of delivering a heralded single-photon given a heralding event), it also needs to maintain the high extinction ratio necessary to reject the noises from the pump and the unwanted non-linear processes [3,5] that may be present in the chip. The development of a range of filtering strategies and designs-based on existing solutions in literature and developed jointly with the SNSPDs fabricated in-house-will be the focus of year 2. If everything goes according to plan, in year 3, the final PIC for a single-photon source with on-chip heralding detector may be designed, fabricated and post-processed, using the components from the previous years, and hopefully, the on-chip heralding will be demonstrated.