Low-power logic design using structured logic blocks

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The semiconductor industry continues to shrink the size of the transistor every two or three years. This allows more transistors to be placed on the same chip. At this point, transistors are considered to be almost free. However, the way that integrated circuits are fabricated is getting more complex and new problems have surfaced due to the fine geometries. Furthermore, the chips themselves are taking more time to design, incur higher costs, are difficult to test and consume more power. New design methods and software tools are needed to address all these issues. This research investigates an alternative method to designing logic circuits that lends itself to ease of implementation, test and fabrication. Since transistors are cheap, it is time to re-examine and improve structured logic arrays and then assess their suitability as a mainstream logic design style. The advantage of a structured logic array is that it has a regular layout that is easier to fabricate and it also has features that make design automation relatively straight-forward. It is also amenable to automatic testing and correction using built-in self-test and self-repair techniques. However, these arrays have overhead in terms of timing, power and area.  This research will attempt to improve these three aspects of logic arrays and determine if they can compete with the standard design techniques. The overall goal is to demonstrate that structured logic arrays are the most viable approach for future chip designs, as the transistors continue to shrink in size.