I-Corps: Tunnel FET-based transistor logic for ultra-low-power applications

I-Corps:适用于超低功耗应用的基于隧道 FET 的晶体管逻辑

基本信息

  • 批准号:
    1806182
  • 负责人:
  • 金额:
    $ 5万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2018
  • 资助国家:
    美国
  • 起止时间:
    2018-01-01 至 2019-06-30
  • 项目状态:
    已结题

项目摘要

The broader impact/commercial potential of this I-Corps project is that the project device has the potential to become the next generation of ultra-low power devices. Tunnel Field Effect Transistors (TFETs), especially those with type III-V heterostructures, are excellent candidates to overcome both size and power scaling issue of Silicon metal?oxide?semiconductor field-effect transistor (Si MOSFET). III-V heterojunction TFET can easily achieve low power consumption by having high on-current and low off-current within a very short range of applied voltage. One of the bottlenecks for III-V materials to become mainstream is the lack of integration with current silicon manufacturing technology. The proposed device demonstrates technology that is compatible with silicon manufacturing technology which has the most commercial impact compared to any other III-V materials devices as it does not require any changes in the existing manufacturing process. By realizing this device, it will open the opportunity to replace the current existing FinFET technology in cellphone and computers, making a new generation of portable devices for logic applications and enabling ever-connected internet of things applications.This I-Corps project proposes to create a low power tunneling field effect transistor (TFET) on a silicon substrate using novel fabrication techniques. The device employs InAs/AlSb/GaSb junction as the tunneling junction. This unique junction produces effective modulation of electron tunneling under control of the applied gate bias. The tunneling barrier AlSb layer is sandwiched between InAs and GaSb. This configuration allows the free band movements between InAs and GaSb. This unique junction is combined with a fin type channel structure to allow effective control over the active channel region by the surrounding gate metals. The fin device architecture will allow excellent gate electro-static control, and combining it with the tunneling mechanism will enable the fabricated devices to achieve a subthreshold slope much smaller than 60mV/dec. Another unique aspect of the proposed design is the use of elevated asymmetric T-shaped source and drain.
该I-Corps项目的更广泛影响/商业潜力在于,该项目设备有可能成为下一代超低功耗设备。隧道场效应晶体管(TFFET),特别是那些具有III-V型异质结构的TFFET,是克服硅金属尺寸和功率缩放问题的优秀候选者。氧化物?半导体场效应晶体管(Si MOSFET)。III-V异质结TFET可以通过在非常短的施加电压范围内具有高导通电流和低截止电流而容易地实现低功耗。III-V族材料成为主流的瓶颈之一是缺乏与当前硅制造技术的集成。申报器械证明了与硅制造技术兼容的技术,与任何其他III-V族材料器械相比,硅制造技术具有最大的商业影响,因为它不需要对现有制造工艺进行任何变更。通过实现这种器件,它将有机会取代目前手机和计算机中现有的FinFET技术,制造新一代用于逻辑应用的便携式设备,并实现不断连接的物联网应用。这个I-Corps项目提出使用新的制造技术在硅衬底上制造低功率隧道场效应晶体管(TFET)。该器件采用InAs/AlSb/GaSb结作为隧道结。这种独特的结在施加的栅极偏压的控制下产生电子隧穿的有效调制。隧道势垒AlSb层夹在InAs和GaSb之间。这种配置允许InAs和GaSb之间的自由带移动。这种独特的结与鳍型沟道结构相结合,以允许通过周围的栅极金属对有源沟道区进行有效控制。鳍器件的架构将允许出色的栅极静电控制,并结合它与隧穿机制将使制造的设备,以实现远小于60 mV/dec的亚阈值斜率。另一个独特的方面,所提出的设计是使用升高的非对称T形源极和漏极。

项目成果

期刊论文数量(3)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Effect of bistrifluoromethane sulfonimide treatment on nickel/InAs contacts
双三氟甲磺酰亚胺处理对镍/InAs 触点的影响
  • DOI:
    10.1007/s00339-019-2705-7
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Shariar, Kazy F.;Lin, Guangyang;Wang, Zijian;Cui, Peng;Zhang, Jie;Opila, Robert;Zeng, Yuping
  • 通讯作者:
    Zeng, Yuping
InAs FinFETs Performance Enhancement by Superacid Surface Treatment
通过超酸表面处理增强 InAs FinFET 性能
  • DOI:
    10.1109/ted.2019.2901281
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    3.1
  • 作者:
    Zeng, Yuping;Khandelwal, Sourabh;Shariar, Kazy F.;Wang, Zijian;Lin, Guangyang;Cheng, Qi;Cui, Peng;Opila, Robert;Balakrishnan, Ganesh;Addamane, Sadhvikas
  • 通讯作者:
    Addamane, Sadhvikas
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Yuping Zeng其他文献

Fabrication of Germanium Tin Microstructures Through Inductively Coupled Plasma Dry Etching
通过感应耦合等离子体干法刻蚀制造锗锡微结构
  • DOI:
  • 发表时间:
    2021
  • 期刊:
  • 影响因子:
    2.4
  • 作者:
    Guangyang Lin;Peng Cui;Tao Wang;R. Hickey;Jie Zhang;Haochen Zhao;J. Kolodzey;Yuping Zeng
  • 通讯作者:
    Yuping Zeng
Performance enhancement of monolayer MoS2 transistors by atomic layer deposition of high-k dielectric assisted by Al2O3 seed layer
Al2O3 种子层辅助高 k 电介质原子层沉积提高单层 MoS2 晶体管的性能
  • DOI:
    10.1088/1361-6463/ab605b
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Guangyang Lin;Meng;Meng Jia;Jie Zhang;Peng Cui;Lincheng Wei;Haochen Zhao;A. T. Johnson;L. Gundlach;Yuping Zeng
  • 通讯作者:
    Yuping Zeng
Liability of Foreignness and the Constitutive Legitimation of Foreign Firms in a Host Country
外国人的责任和外国公司在东道国的构成合法性
  • DOI:
    10.1016/j.jwb.2020.101111
  • 发表时间:
    2020-06
  • 期刊:
  • 影响因子:
    8.9
  • 作者:
    Yuping Zeng;Dean Xu
  • 通讯作者:
    Dean Xu
Effects of whisker surface modification on microstructures, mechanical and thermal properties of β-Si3N4 whiskers reinforced Al matrix composites
晶须表面改性对β-Si3N4晶须增强铝基复合材料微观结构、力学性能和热性能的影响
  • DOI:
    10.1016/j.matdes.2018.08.055
  • 发表时间:
    2018-12
  • 期刊:
  • 影响因子:
    8.4
  • 作者:
    Chenxu Zhang;Dongxu Yao;Jinwei Yin;Kaihui Zuo;Yongfeng Xia;Hanqin Liang;Yuping Zeng
  • 通讯作者:
    Yuping Zeng
The effect of foreign firms’ population density on exit likelihood in a host country
外国公司人口密度对东道国退出可能性的影响
  • DOI:
    10.1108/md-03-2019-0354
  • 发表时间:
    2019-11
  • 期刊:
  • 影响因子:
    4.6
  • 作者:
    Yuping Zeng;Dean Xu
  • 通讯作者:
    Dean Xu

Yuping Zeng的其他文献

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{{ truncateString('Yuping Zeng', 18)}}的其他基金

Collaborative Research: FuSe:Substrate-inverted Multi-Material Integration Technology
合作研究:FuSe:衬底倒置多材料集成技术
  • 批准号:
    2328840
  • 财政年份:
    2023
  • 资助金额:
    $ 5万
  • 项目类别:
    Continuing Grant
CAREER: Enhancing GaN-on-Si high electron mobility transistor technology for high frequency and high power applications
职业:增强用于高频和高功率应用的硅基氮化镓高电子迁移率晶体管技术
  • 批准号:
    2239302
  • 财政年份:
    2023
  • 资助金额:
    $ 5万
  • 项目类别:
    Continuing Grant

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FET:小型:CMOS X:集成 CMOS 和压控磁隧道结,用于概率计算
  • 批准号:
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Proposal of integratable two dimensional tunnel FET structure and demonstration of its ultra-low power operation
可集成二维隧道FET结构的提出及其超低功耗操作的演示
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Integration of 2 dimensional tunnel FET for ultra-low power consumption system
集成二维隧道 FET,实现超低功耗系统
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    2022
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CISE-ANR: FET: Small: Hybrid Stochastic Tunnel Junction Circuits for Optimization and Inference
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Development of ultra-low power neural network chips using non-volatile tunnel FET memory
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Inverstigation on vertical tunnel FET using Si/III-V heterojunction and their three-dimensional integrated circuit applications
Si/III-V异质结垂直隧道场效应管及其三维集成电路应用研究
  • 批准号:
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基于了解 2D 异质界面特性的 2D 隧道 FET
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The realization of steep slope tunnel FET on Ge-on-Insulator substrate
Ge-on-Insulator衬底上陡坡隧道FET的实现
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Heavy-ion induced current in Tunnel FET
隧道 FET 中的重离子感应电流
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