Area and power efficient interconnect architecture for multi-bit processing on FPGAs

现场可编程门阵列(FGA)是为实现数字系统而设计的器件。它们针对硬件算法进行了优化，并具有能够在几分之一秒内更改其功能的额外优势。作为面向硬件和可编程的，现场可编程门阵列提供了许多应用所必需的独特的性能和功能的混合。拥有超过8万个设计起点和每年40亿美元的销售额，现场可编程门阵列已经成为最受欢迎的计算媒体之一。众所周知，现场可编程门阵列的可编程性使得他们的设计特别具有挑战性。通常只有25%的现场可编程门阵列面积用于执行计算。剩下的75%用于将计算元素连接在一起。因此，FPGA互连的设计可以和计算元件的设计一样重要。他说，这项研究的目标是增加FPGA互连的面积和功率效率。该领域现有的几乎所有研究都涉及一次处理一点信息的计算元件。然而，现代的现场可编程门阵列也包含被设计为同时处理多比特信息的元件。这些多比特处理元件的使用增加了给问题带来了新的未探索的方面和变量。在这项工作中，我们将重点研究多比特处理元件的两个独特属性-它们的信号的相关行为和它们的大小变化。首先，我们将利用相关行为来利用互连的面积和功率效率的转换能力。然后，我们将研究将不同大小的计算元素连接在一起的最有效方法。最后，我们将研究如何将单比特处理单元分组为多比特处理单元，以提高它们的互连效率。

Field-Programmable Gate Arrays (FPGAs) are devices that are designed to implement digital systems. They are optimized for hardware algorithms and have the added advantages of being able to change their functionalities in a fraction of a second. Being both hardware-oriented and programmable, FPGAs provide a unique blend of performance and functionality that is essential to many applications. With over 80,000 design-starts and $4 billion in sales annually, FPGAs have become one of the most popular computing media.     The programmability of FPGAs has made their design particularly challenging. Typically only 25% of FPGA area is used to perform computation. The remaining 75% is used to connect the computing elements together. Consequently, the design of FPGA interconnects can be as important as the design of the computing elements.     The goal of this research is to increase the area and power efficiency of FPGA interconnects. Virtually all existing investigations in the field have dealt with computing elements that process one bit of information at a time. Modern FPGAs, however, also contain elements that are designed to process multiple-bits of information simultaneously. The increased use of these multi-bit processing elements has introduced new unexplored aspects and variables to the problem.     In this work, we will focus on two unique properties of the multi-bit processing elements --- the correlated behaviours of their signals and their size variation. First, we will take advantage of the correlated behaviours to exploit the shift capabilities of interconnects for area and power efficiency. Then, we will investigate the most efficient method of connecting computing elements of various sizes together. Finally, we will study how the single-bit processing elements can be grouped into multi-bit processing units to improve the efficiency of their interconnects.