Area and power efficient interconnect architecture for multi-bit processing on FPGAs

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Field-Programmable Gate Arrays (FPGAs) are devices that are designed to implement digital systems. They are optimized for hardware algorithms and have the added advantages of being able to change their functionalities in a fraction of a second. Being both hardware-oriented and programmable, FPGAs provide a unique blend of performance and functionality that is essential to many applications. With over 80,000 design-starts and $4 billion in sales annually, FPGAs have become one of the most popular computing media.     The programmability of FPGAs has made their design particularly challenging. Typically only 25% of FPGA area is used to perform computation. The remaining 75% is used to connect the computing elements together. Consequently, the design of FPGA interconnects can be as important as the design of the computing elements.     The goal of this research is to increase the area and power efficiency of FPGA interconnects. Virtually all existing investigations in the field have dealt with computing elements that process one bit of information at a time. Modern FPGAs, however, also contain elements that are designed to process multiple-bits of information simultaneously. The increased use of these multi-bit processing elements has introduced new unexplored aspects and variables to the problem.     In this work, we will focus on two unique properties of the multi-bit processing elements --- the correlated behaviours of their signals and their size variation. First, we will take advantage of the correlated behaviours to exploit the shift capabilities of interconnects for area and power efficiency. Then, we will investigate the most efficient method of connecting computing elements of various sizes together. Finally, we will study how the single-bit processing elements can be grouped into multi-bit processing units to improve the efficiency of their interconnects.