Area and power efficient interconnect architecture for multi-bit processing on FPGAs

用于 FPGA 上多位处理的面积和功率高效互连架构

• 批准号: 327691-2007
• 负责人: Ye, Andy
• 金额: $ 1.38万
• 依托单位: Ryerson University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2009
• 资助国家: 加拿大
• 起止时间: 2009-01-01 至 2010-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=428974
• 关键词: Area; power; efficient; interconnect; architecture

Field-Programmable Gate Arrays (FPGAs) are devices that are designed to implement digital systems. They are optimized for hardware algorithms and have the added advantages of being able to change their functionalities in a fraction of a second. Being both hardware-oriented and programmable, FPGAs provide a unique blend of performance and functionality that is essential to many applications. With over 80,000 design-starts and $4 billion in sales annually, FPGAs have become one of the most popular computing media.

现场可编程门阵列（FPGA）是设计用于实现数字系统的器件。它们针对硬件算法进行了优化，并且具有能够在几分之一秒内更改其功能的额外优势。FPGA既是面向硬件的，又是可编程的，它提供了一种独特的性能和功能的结合，这对许多应用至关重要。FPGA每年有超过80，000个设计启动和40亿美元的销售额，已成为最受欢迎的计算媒体之一。