Gate drive circuits for GaN power transistors

GaN功率晶体管的栅极驱动电路

• 批准号: 452953-2013
• 负责人: Ng, WaiTung
• 金额: $ 1.82万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Engage Grants Program
• 财政年份: 2013
• 资助国家: 加拿大
• 起止时间: 2013-01-01 至 2014-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=541198
• 关键词: Gate; drive; circuits; GaN; power

GaN power transistors are the next generation power semiconductor devices with significant performance improvement over traditional silicon technology. In order to fully exploit the high switching speed, high breakdown voltage, and low on-resistance of the GaN power devices, a dedicated gate driving scheme is critical. The primary objectives of the gate driving circuit are to provide fast, efficient and quiet switching of the GaN power devices. Traditional gate driving circuit design strategy involves a compromise by slowing down the turn-on and turn-off of the power devices to supress ringing at the gate terminal and at the output switching node. This results in a trade-off between switching loss and the EMI spectrum. Unfortunately, due to these compromised driving characteristics, the full potential of the GaN power devices cannot be realized. The proposed project is aimed at demonstrating an effective gate driving scheme for GaN power transistors that can provide fast switching speed and optimized dead-time to achieve high energy efficiency and EMI suppression simultaneously. The target GaN power transistors are the 650V/18A/120mOhms GaN cascode from GaN Systems, Ottawa, Canada. An existing custom gate driver IC with dynamically adjustable driving strength will be used for this experiment. This custom gate driver IC was designed previously by the applicant and his team. It is implemented using a 0.18µm 40V HV-CMOS technology. The main focus is to investigate the proper timing and driving strength combinations that will yield the most optimal switching performance for GaN power transistors. A test bench consisting of a totem pole half-bridge output stage with two depletion mode GaN power transistors, each with a low voltage cascode connected n-channel power MOSFET to provide normally off operation, will be constructed. An FPGA development platform will be used to generate the necessary gate drive signals. The measurement results will allow us to gain critical understanding on how to design a dedicated gate driver IC for GaN power transistors with optimized performance.

GaN功率晶体管是下一代功率半导体器件，与传统的硅技术相比具有显著的性能改进。为了充分利用GaN功率器件的高开关速度、高击穿电压和低导通电阻，专用栅极驱动方案至关重要。栅极驱动电路的主要目标是提供GaN功率器件的快速、高效和安静的开关。传统的栅极驱动电路设计策略涉及通过减慢功率器件的导通和关断来抑制栅极端子和输出开关节点处的振铃的折衷。这导致开关损耗和EMI频谱之间的折衷。不幸的是，由于这些折衷的驱动特性，GaN功率器件的全部潜力无法实现。该项目旨在为GaN功率晶体管演示一种有效的栅极驱动方案，该方案可以提供快速的开关速度和优化的死区时间，从而同时实现高能效和EMI抑制。目标GaN功率晶体管是来自加拿大渥太华的GaN Systems的650 V/18 A/120 mOhms GaN共源共栅。现有的定制栅极驱动器IC与动态可调的驱动强度将用于此实验。该定制栅极驱动器IC由申请人及其团队先前设计。它采用0.18µm 40 V HV-CMOS技术实现。主要重点是研究适当的时序和驱动强度组合，以获得GaN功率晶体管的最佳开关性能。将构建一个由图腾柱半桥输出级和两个耗尽型GaN功率晶体管组成的测试台，每个晶体管都有一个低电压共源共栅连接的n沟道功率MOSFET，以提供常关操作。FPGA开发平台将用于生成必要的栅极驱动信号。测量结果将使我们能够深入了解如何设计具有优化性能的GaN功率晶体管专用栅极驱动器IC。