Gate drive circuits for GaN power transistors

点击翻译按钮获取中文摘要

GaN power transistors are the next generation power semiconductor devices with significant performance improvement over traditional silicon technology. In order to fully exploit the high switching speed, high breakdown voltage, and low on-resistance of the GaN power devices, a dedicated gate driving scheme is critical. The primary objectives of the gate driving circuit are to provide fast, efficient and quiet switching of the GaN power devices. Traditional gate driving circuit design strategy involves a compromise by slowing down the turn-on and turn-off of the power devices to supress ringing at the gate terminal and at the output switching node. This results in a trade-off between switching loss and the EMI spectrum. Unfortunately, due to these compromised driving characteristics, the full potential of the GaN power devices cannot be realized. The proposed project is aimed at demonstrating an effective gate driving scheme for GaN power transistors that can provide fast switching speed and optimized dead-time to achieve high energy efficiency and EMI suppression simultaneously. The target GaN power transistors are the 650V/18A/120mOhms GaN cascode from GaN Systems, Ottawa, Canada. An existing custom gate driver IC with dynamically adjustable driving strength will be used for this experiment. This custom gate driver IC was designed previously by the applicant and his team. It is implemented using a 0.18µm 40V HV-CMOS technology. The main focus is to investigate the proper timing and driving strength combinations that will yield the most optimal switching performance for GaN power transistors. A test bench consisting of a totem pole half-bridge output stage with two depletion mode GaN power transistors, each with a low voltage cascode connected n-channel power MOSFET to provide normally off operation, will be constructed. An FPGA development platform will be used to generate the necessary gate drive signals. The measurement results will allow us to gain critical understanding on how to design a dedicated gate driver IC for GaN power transistors with optimized performance.