Study Single Event Effects in Microelectronics

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Silicon technologies have been the dominant platform for the majority of the electronic devices in industry. The silicon technology scaling has significantly improved the performance of the integrated circuits (ICs). However, the scaling also brought a number of reliability issues that have previously been less of a concern. Due to the small device dimension and low operating voltages, nanoscale ICs have become highly sensitive to operational disturbances. These disturbances, especially those caused by single event effects (SEEs) due to energetic particles in ICs, can introduce transient pulses in logic circuit nodes or upset data in storage cells. Their impact can range from a single data corruption to a severe system crash. For example, Sun Microsystems had to recall their flagship servers in 2000 due to sudden and mysterious crashes which were caused by cosmic particles. Even for ICs in terrestrial environments, the error rates caused by SEEs can be 100 times higher than those from hard failures such as device wear out. The objectives of the proposed research program are to study the SEEs in microelectronics, hence advise cost-effective mitigation solutions to achieve reliable operations for electronic circuits and systems. Digital and analog circuits with/without SEE-hardening techniques will be designed and fabricated in test chips using advanced silicon technologies. Ion beams (protons and heavy ions) will be used to evaluate their performance in term of SEE tolerance. An on-campus pulsed laser facility has been established and will be used as an investigation tool to characterize SEEs in the test chips, since it can precisely induce SEEs in the ICs at a designated location and time. In addition, device- and circuit-level simulation tools will be used to model and characterize the performance of the test circuits. The simulation results will be used to correlate with the laser and ion radiation results, which will provide insight understanding and information of SEEs in ICs. The proposed program will develop SEE-tolerant technologies for Canadian industry to improve reliability of microelectronics. Through the research program, a number of highly skilled personnel will be trained in this highly demand field.