Study single event effects in logic circuits with 28nm CMOS bulk and SOI technologies

使用 28nm CMOS 体和 SOI 技术研究逻辑电路中的单粒子效应

• 批准号: 460881-2013
• 负责人: Chen, Li
• 金额: $ 6.11万
• 依托单位: University of Saskatchewan
• 依托单位国家: 加拿大
• 项目类别: Collaborative Research and Development Grants
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=576620
• 关键词: Study; single; event; effects; logic

Over the last four decades, silicon technology scaling has remarkably improved the integrated circuits (ICs) by increasing the transistor density and operating frequency while reducing the cost and energy consumption per transistor. However, the scaling of silicon technologies makes ICs more vulnerable to single event effects (SEEs) induced by energetic particles. In a well-designed IC, soft errors induced by SEEs appear to be the most troublesome both in terrestrial and high altitude or space environment. Storage cells are one of the major sources of soft errors in digital systems, and the soft error rates can be in 3 order differences for the designs from different vendors. Silicon-on-insulator (SOI) process has emerging to be a promising technology for reducing soft error rates in electronic systems. The objectives of the proposed project are to develop fault-tolerant logic circuits that are fabricated with the most advanced CMOS technologies in order to reduce the soft error rate in Cisco's switches and other electronic products. We will study SEE in both advanced bulk and SOI CMOS technologies (28nm process) and aim to develop fault-tolerant digital storage and sensing circuits. Various techniques including both layout and design techniques will be used to develop the fault-tolerant storage cells. Device and schematic simulation tools will be used for the investigation, so that SEE mitigation methods can be effectively developed. The fabricated test chips will be tested with pulsed laser, heavy ion, proton and neutron beams to verify the effectiveness of the designs. The results from different testing facilities will also be correlated. One PDF, two Ph.D. students and one mater's student will be trained to advance the technology and to work closely with the industrial partners. The research results will result in patentable technologies and publications in related journals and conferences. The Canadian industry partner (Cisco Canada) can adopt the technologies developed from this project to improve the reliability of their products such as switches and linecards. The project will also enhance the capability and expertise of the research group in the area of microelectronics reliability at the University of Saskatchewan.

在过去的四十年中，硅技术微缩通过增加晶体管密度和工作频率，同时降低每个晶体管的成本和能耗，显着改进了集成电路（IC）。然而，硅技术的规模化使得 IC 更容易受到高能粒子引起的单粒子效应 (SEE) 的影响。在精心设计的 IC 中，SEE 引起的软错误似乎在陆地和高空或太空环境中都是最麻烦的。存储单元是数字系统中软错误的主要来源之一，不同供应商的设计的软错误率可能有3个数量级的差异。绝缘体上硅 (SOI) 工艺已成为降低电子系统软错误率的一项有前途的技术。该项目的目标是开发采用最先进的 CMOS 技术制造的容错逻辑电路，以降低思科交换机和其他电子产品中的软错误率。 我们将研究先进体硅和 SOI CMOS 技术（28 纳米工艺）中的 SEE，旨在开发容错数字存储和传感电路。包括布局和设计技术在内的各种技术将用于开发容错存储单元。器件和原理图仿真工具将用于研究，以便有效地开发SEE缓解方法。制造的测试芯片将使用脉冲激光、重离子、质子和中子束进行测试，以验证设计的有效性。不同测试机构的结果也将相互关联。一份 PDF，两份博士论文。学生和一名硕士生将接受培训以推进技术并与工业合作伙伴密切合作。研究成果将产生可专利技术并在相关期刊和会议上发表。加拿大行业合作伙伴（思科加拿大）可以采用该项目开发的技术来提高其交换机和线卡等产品的可靠性。该项目还将增强萨斯喀彻温大学研究小组在微电子可靠性领域的能力和专业知识。