Development of low-voltage and low-power mixed-signal ICs using nano-scale multiple gate field-effect transistors

使用纳米级多栅极场效应晶体管开发低电压和低功耗混合信号IC

• 批准号: 342879-2012
• 负责人: ElSankary, Kamal
• 金额: $ 1.31万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=572511
• 关键词: Development; low; voltage; power; mixed

The low-power and cost-effective Complementary Metal-Oxide-Semiconductor (CMOS) devices have forced the analog designers to develop integrated circuits (ICs) using digital CMOS technologies. Conventional nano-scale planar CMOS devices suffer from undesirable short-channel effects, such as high drain induced barrier lowering, substantial leakage currents due to threshold voltage roll-off, lower intrinsic gain, lower output impedance, lower dynamic range and poorer device matching. These non-idealities eventually degrade the performance of CMOS devices and pose a serious threat to ICs' performance. The Multiple gate field-effect transistors, such as Fin-shaped Field Effect Transistors (FinFETs), are emerging as the most promising replacement for planar CMOS in sub-32nm technologies. In fact, FinFET technology offers interesting features such as tight channel control to mitigate short channel effects, and steeper sub-threshold slope. Despite the advantages of multi-gate technologies, new design challenges arise particularly for analog, mixed-signal and radio frequency (RF) circuits. FinFETs suffer from larger parasitic compared to planar CMOS transistors. The narrow fin width increases the source and drain resistances and that result in degrading the high frequency and noise performance of FinFETs. Also the empty region between the gate and the source/drain causes a large increase in the fringe capacitors of the transistor and consequently reduces the speed of RF applications. FinFET devices also show new undesirable effects that have to be taking into consideration while designing analog and mixed-signal circuits; namely self-heating and hysteresis effect. Moreover, accurate physical characterization of FinFET devices represents a tremendous challenge for analog designer and new optimized layout techniques are also necessary to fully benefit from this advanced technology. As a result to enjoy the merit of multi-gate field-effect transistors, the objective of this proposal is to develop novel design methodologies for high performance analog, RF and mixed signal circuits using FinFETs.

低功耗、低成本的互补金属氧化物半导体（CMOS）器件迫使模拟设计人员使用数字CMOS技术开发集成电路（IC）。传统的纳米级平面CMOS器件遭受不期望的短沟道效应，例如高漏极感应势垒降低、由于阈值电压滚降而导致的大量泄漏电流、较低的固有增益、较低的输出阻抗、较低的动态范围和较差的器件匹配。这些非理想性最终会降低CMOS器件的性能，并对集成电路的性能构成严重威胁。 多栅场效应晶体管，如鳍形场效应晶体管（FinFET），正在成为最有前途的替代平面CMOS在亚32纳米技术。事实上，FinFET技术提供了一些有趣的特性，例如可以减轻短沟道效应的严格沟道控制，以及更陡的亚阈值斜率。 尽管多门技术具有诸多优势，但新的设计挑战尤其出现在模拟、混合信号和射频（RF）电路方面。与平面CMOS晶体管相比，FinFET遭受更大的寄生。窄鳍宽度增加了源极和漏极电阻，导致FinFET的高频和噪声性能下降。此外，栅极和源极/漏极之间的空区域导致晶体管的边缘电容器的大幅增加，从而降低了RF应用的速度。FinFET器件还显示出在设计模拟和混合信号电路时必须考虑的新的不期望的效应;即自加热和滞后效应。此外，FinFET器件的精确物理特性对模拟设计人员来说是一个巨大的挑战，新的优化布局技术也是必要的，以充分受益于这种先进的技术。 因此，享受多栅极场效应晶体管的优点，本建议的目标是开发新的设计方法，高性能的模拟，RF和混合信号电路使用FinFET。