Design-for-test techniques for system-on-chip devices

在单个芯片上实现更多系统功能的趋势导致了包含各种知识产权核心的集成电路的发展，例如逻辑块，模拟和射频核心以及微机电系统（MEMS）。三维集成电路被许多专家认为是集成电路设计技术的突破。3D集成电路架构具有显著提高集成系统性能的潜力。然而，如果在克服开发微系统测试解决方案的挑战方面没有重大进展，这项新技术的成功将不会完全实现。

The trend towards more system functionality on a single chip has led to the development of integrated circuits containing a variety of intellectual-property cores such as logic blocks, analog and RF cores as well as Microelectromechanical Systems (MEMS). Three dimensional IC integration is considered by many experts to be a breakthrough in the IC design technology. 3D IC architecture has the potential to dramatically improve the performance of integrated systems. However, the success of this new technology will not be fully materialized without significant progress in overcoming the challenges of developing test solutions for Microsystems. Distributed test systems enabled by application of Design-for-Test (DFT) techniques are considered feasible and cost effective solutions to the problem of test for modern integrated circuits and systems. DFT techniques are well established and widely used for digital circuits. However, they are at the early stages of development for MEMS and three dimensional devices. The test techniques developed over years for integrated circuits provide a good basis for developing test solutions for MEMS and 3D ICs. The main objective of this work is to advance the design-for-test techniques for analog/RF circuits, MEMS structures and 3D ICs to reduce the overall manufacturing cost of modern integrated circuits and systems. The specific aims of this research proposal are to: (a)-Design a MEMS based Micro-Probes for Three Dimensional ICs (b)-Develop a Built-in Self-Test (BIST) for CMOS-MEMS Sensors (c)-Implement an alternate testing method for RF circuits (d)-Design of test interface circuits to reduce the undesired effects of transmission lines