High-Speed Low-Power Data Acquisition and Serial Data Communications

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As the industry moves into the very deep submicron stages of integrated circuit device scaling, new techniques are being sought to improve performance of all types of analog and digital circuits. Vast amounts of digital logic can be placed in small chip area, allowing digital correction of analog circuit errors resulting from PVT (fabrication process, supply voltage and temperature) variations on circuit behavior. At the same time, the very small devices have small parasitic capacitances and resistances, resulting in much-improved switching speeds and analog bandwidths. Silicon-on-insulator (SOI) technology is particularly attractive, and results in lower manufacturing costs compared to bulk CMOS due to substantially lower mask count requirements during manufacture. These facts have lead to an examination of circuit techniques that move away from conventional voltage-based circuits to circuits that exploit the small switching times and timing differences that are available, to realize circuits such as Analog-to-Digital Converters (ADCs) and Serializer-Deserializer (SerDes) data communications circuits that are ubiquitous in modern electronic systems. Over the past 5 years, we have pioneered the first low-power time-based GigaSample/sec ADCs, enhancing performance using digital background correction of errors due to PVT variations, and also proposed new time-based Gigabit/sec SerDes architectures. Because this approach is new and exploratory, much work remains to be done in order to establish a comparison of performance limits compared to voltage-based circuits, and requires circuit fabrication and testing in the latest scaled SOI technologies. The ADCs that we have designed so far have a unique added advantage that an analog front-end voltage-to-time conversion circuit (a VTC) can be physically separated from a back-end Time-to-Digital Conversion circuit (a TDC), allowing designers to physically remove the noise-producing high-speed switching circuits from the sensitive analog front end, thereby improving the effective number of bits (ENOB) achieved by the converters. This could have special advantages in applications such as those in the world's next-generation radio telescope called the Square Kilometer Array, a 20-country international project in which we are heavily involved, and which will require possibly millions of low power, ultra-low-noise, ultra-high-gain, wideband signal chains for each antenna element in the vast array. The proposed circuits will also find applications in data and voice communications in next-generation software-defined radio, and in all aspects of data acquisition and transmission. In addition to the ADC research, I propose to examine new ways of increasing data throughput rates in SerDes systems without requiring more complicated and power-hungry circuits to transmit and receive the data. We have shown both theoretically and experimentally using field-programmable gate arrays (FPGAs) that high data rates can be achieved in time-based circuits using significantly lower clock rates that are required in conventional voltage-based SerDes systems. We have new ideas for increasing the data rates further without having to increase clock frequency. To compare performance with conventional systems, we need to design, fabricate and test complete chipsets in 28nm and smaller technologies. The ADCs can also be used as direct-digitizing receivers in conventional SerDes systems, and industrial firms are now moving in that direction for next-generation SerDes products. New high-performance TDCs are also being investigated by my research group, and those circuits have direct applications in Phase-locked-Loop (PLL) frequency synthesizers. We have a well-equipped measurement laboratory to support this research.