High-Speed Low-Power Data Acquisition and Serial Data Communications

高速低功耗数据采集和串行数据通信

• 批准号: RGPIN-2014-03788
• 负责人: Haslett, James
• 金额: $ 2.7万
• 依托单位: University of Calgary
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2014
• 资助国家: 加拿大
• 起止时间: 2014-01-01 至 2015-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=566087
• 关键词: Speed; Low; Power; Data; Acquisition

As the industry moves into the very deep submicron stages of integrated circuit device scaling, new techniques are being sought to improve performance of all types of analog and digital circuits. Vast amounts of digital logic can be placed in small chip area, allowing digital correction of analog circuit errors resulting from PVT (fabrication process, supply voltage and temperature) variations on circuit behavior. At the same time, the very small devices have small parasitic capacitances and resistances, resulting in much-improved switching speeds and analog bandwidths. Silicon-on-insulator (SOI) technology is particularly attractive, and results in lower manufacturing costs compared to bulk CMOS due to substantially lower mask count requirements during manufacture. These facts have lead to an examination of circuit techniques that move away from conventional voltage-based circuits to circuits that exploit the small switching times and timing differences that are available, to realize circuits such as Analog-to-Digital Converters (ADCs) and Serializer-Deserializer (SerDes) data communications circuits that are ubiquitous in modern electronic systems. Over the past 5 years, we have pioneered the first low-power time-based GigaSample/sec ADCs, enhancing performance using digital background correction of errors due to PVT variations, and also proposed new time-based Gigabit/sec SerDes architectures. Because this approach is new and exploratory, much work remains to be done in order to establish a comparison of performance limits compared to voltage-based circuits, and requires circuit fabrication and testing in the latest scaled SOI technologies. The ADCs that we have designed so far have a unique added advantage that an analog front-end voltage-to-time conversion circuit (a VTC) can be physically separated from a back-end Time-to-Digital Conversion circuit (a TDC), allowing designers to physically remove the noise-producing high-speed switching circuits from the sensitive analog front end, thereby improving the effective number of bits (ENOB) achieved by the converters. This could have special advantages in applications such as those in the world's next-generation radio telescope called the Square Kilometer Array, a 20-country international project in which we are heavily involved, and which will require possibly millions of low power, ultra-low-noise, ultra-high-gain, wideband signal chains for each antenna element in the vast array. The proposed circuits will also find applications in data and voice communications in next-generation software-defined radio, and in all aspects of data acquisition and transmission. In addition to the ADC research, I propose to examine new ways of increasing data throughput rates in SerDes systems without requiring more complicated and power-hungry circuits to transmit and receive the data. We have shown both theoretically and experimentally using field-programmable gate arrays (FPGAs) that high data rates can be achieved in time-based circuits using significantly lower clock rates that are required in conventional voltage-based SerDes systems. We have new ideas for increasing the data rates further without having to increase clock frequency. To compare performance with conventional systems, we need to design, fabricate and test complete chipsets in 28nm and smaller technologies. The ADCs can also be used as direct-digitizing receivers in conventional SerDes systems, and industrial firms are now moving in that direction for next-generation SerDes products. New high-performance TDCs are also being investigated by my research group, and those circuits have direct applications in Phase-locked-Loop (PLL) frequency synthesizers. We have a well-equipped measurement laboratory to support this research.

随着工业进入集成电路器件缩放的非常深的亚微米阶段，正在寻求新技术来提高所有类型的模拟和数字电路的性能。大量的数字逻辑可以放置在小芯片面积上，允许对由电路行为上的PVT（制造工艺、电源电压和温度）变化引起的模拟电路误差进行数字校正。同时，这些非常小的器件具有很小的寄生电容和电阻，从而大大提高了开关速度和模拟带宽。绝缘体上硅（SOI）技术特别有吸引力，并且由于在制造期间实质上更低的掩模数量要求，与体CMOS相比导致更低的制造成本。这些事实已经导致对电路技术的检查，该电路技术从传统的基于电压的电路转移到利用可用的小的切换时间和定时差的电路，以实现诸如在现代电子系统中普遍存在的模数转换器（ADC）和串行器-解串器（SerDes）数据通信电路的电路。在过去的5年中，我们率先推出了第一款低功耗时基千兆采样/秒ADC，通过对PVT变化引起的误差进行数字背景校正来增强性能，并提出了新的时基千兆/秒SerDes架构。由于这种方法是新的和探索性的，为了建立与基于电压的电路相比的性能限制的比较，还有很多工作要做，并且需要在最新的缩放SOI技术中进行电路制造和测试。迄今为止，我们设计的ADC具有独特的附加优势，即模拟前端电压-时间转换电路（VTC）可以与后端时间-数字转换电路（TDC）物理分离，使设计人员能够从敏感的模拟前端物理移除产生噪声的高速开关电路，从而提高转换器实现的有效位数（ENOB）。这在应用中可能具有特殊的优势，例如在世界上被称为平方公里阵列的下一代射电望远镜中的应用，这是一个20个国家的国际项目，我们积极参与其中，并且可能需要数百万个低功耗，超低噪声，超高增益，宽带信号链用于巨大阵列中的每个天线元件。所提出的电路还将在下一代软件定义无线电的数据和语音通信以及数据采集和传输的各个方面中找到应用。除了ADC的研究，我建议研究在SerDes系统中提高数据吞吐率的新方法，而不需要更复杂和功耗高的电路来发送和接收数据。我们已经在理论上和实验上使用现场可编程门阵列（FPGA），高数据速率可以实现在基于时间的电路使用显着降低时钟速率，在传统的基于电压的SerDes系统所需的。我们有了新的想法，可以在不增加时钟频率的情况下进一步提高数据速率。为了与传统系统进行性能比较，我们需要设计、制造和测试28纳米及更小技术的完整芯片组。ADC还可以用作传统SerDes系统中的直接数字化接收器，工业公司现在正朝着下一代SerDes产品的方向发展。我的研究小组也在研究新的高性能TDC，这些电路直接应用于锁相环（PLL）频率合成器。我们有一个设备齐全的测量实验室来支持这项研究。