Digital and Memory Circuits in nano-scale CMOS Technologies

以最先进的技术实现健壮的集成电路正变得越来越困难。工艺的规模化使得晶体管容易受到工艺变化的影响，单个晶体管的不正确运行可能会导致包含数百万个晶体管的芯片故障。通常使用尽可能小的晶体管尺寸来降低功率、能源消耗，并增加封装密度。不幸的是，尺寸越小的晶体管对工艺变化的敏感度越高。特别是，由于晶体管尺寸最小，低电压、低功率静态随机存取存储器(SRAM)电路表现出更高程度的变化。在这项研究中，我们将研究在功率和电压受限的环境中，数字SRAM电路的可变性感知设计。在微处理器中，多达70%-80%的晶体管位于SRAM中。因此，片上系统(SoC)的各个方面--功率、能量、产量、质量和可靠性都会受到SRAM的影响。 建议的研究有两个主要部分-(A)SRAM电路和(B)逻辑电路。在第一部分中，将对SRAM的几个方面进行调查。这项研究的主要目标是(I)通过架构和电路创新来降低SRAM功耗。我们将设计工作在亚阈值电压下的功能SRAM。(Ii)设计电路技术，以减轻工艺变化对读出放大器等重要SRAM块的影响。我们将研究读出放大器的新结构和电路。(Iii)设计能够从单事件扰乱中恢复的软错误健壮的SRAM单元。在研究的第二部分，我们将研究工作在额定电压下的高速数字电路。对高速电路的研究将需要研究高速逻辑风格。这项工作建立在我们最近对恒定延迟(CD)逻辑风格的研究基础上。加法器等构建模块的设计将展示新逻辑系列在高速应用中的有效性。

Realization of robust integrated circuits in state of the art technologies is becoming increasingly difficult. The technology scaling makes transistors susceptible to process variations, and improper functioning of a single transistor may lead to the chip failure containing several million transistors. Often small as possible transistor sizes are used to reduce power, energy consumption, and to increase the packing density. Unfortunately, transistors with smaller dimensions exhibit a higher susceptibility to process variation. In particular, low-voltage, low-power Static Random Access Memory (SRAM) circuits show higher degree of variation owing to smallest possible transistor dimensions. In this research, we will investigate variability-aware design of digital, SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) - power, energy, yield, quality, and reliability are influenced by SRAMs. The proposed research has two broad segments - (a) SRAM circuits, and (b) logic circuits. In the first segment, few aspects of SRAMs will be investigated. The key objectives of this research are (i) to lower SRAM power consumption through architectural and circuit innovation. We will design functional SRAMs working at sub-threshold voltages. (ii) To devise circuit techniques to alleviate the impact of process variations on important SRAM blocks such as the sense amplifier. We will investigate new architectures and circuits for the sense amplifier. (iii) Design soft error robust SRAM cells that can recover from single event upsets. In the second segment of the research, we will investigate high speed digital circuits working at the nominal voltage. Research on high speed circuits will entail investigation of high speed logic styles. This work builds on our recent research on Constant Delay (CD) logic style. Building blocks such as adder will be designed to demonstrate effectiveness of new logic families for high-speed applications.