高稳定低功耗陡峭斜率免回滞MoS2负电容场效应晶体管研究

以高稳定低功耗陡峭斜率免回滞MoS2负电容(NC) FET为目标，设计新型p++-Si/SiNx/HZO/HfAlON/MoS2堆栈栅结构，围绕HZO铁电层界面工程和铁电电容CFE与MOS电容CMOS匹配工程开展研究。采用NH3等离子体处理与HZO接触的介质和Si衬底，形成稳定的SiNx/HZO/HfAlON夹层结构，利用N结合加固铁电层界面，增强其稳定性，防止氧空位等本征缺陷产生，消除唤醒/印刻效应和极化疲劳，增加介质k值减小EOT；掺Al形成HfAlON介质，可改善介质/MoS2界面质量，提高其结晶温度以利于HZO退火实现铁电性，且能调整Al成份改变k值进而CMOS；通过最佳化HZO退火温度，取得好的铁电性，则可改变其厚度调整CFE，获得CFE和CMOS之间最佳匹配，消除回滞。将研究ALD制备铁电和介质层最佳工艺和条件，研制出MoS2 NCFET原型样品，获得低功耗陡峭斜率免回滞特性。

The project aims at steep-slope hysteresis-free negative-capacitance (NC) MoS2 field-effect transistor (FET) with high performance and low power dissipation. A new stacked gate structure of p++-Si/SiNx/HZO/HfAlON/MoS2 is proposed and prepared, where the ferroelectric-HZO (HfZrOx) and its top-/bottom-interfacial engineering, and capacitance- matching engineering between ferroelectric capacitance (CFE) and MOS capacitance (CMOS) are key research contents. Through using NH3 plasma treatment on the p++-Si substrate and dielectric contacted with HZO, a stable NC structure of SiNx/HZO/HfAlON is formed, so that the hardness and stability of the HZO interfaces are enhanced due to N incorporation. As a result, the formation of the oxygen vacancy can be effectively suppressed, thus free from wake-up/imprinting effects and polarization fatigue, and at the same time, k value of the dielectric layer (HfAlON) can be increased, which is beneficial for reducing EOT and lowing gate leakage. By doping Al in the Hf-based oxynitride, quality of the HfAlON/MoS2 interface can be improved and the crystallization temperature of the dielectric can be increased to facilitate HZO annealing to achieve crystal phase transformation, and moreover, k value of the dielectric can be adjusted by controlling Al content to change CMOS. On the other hand, by optimizing the anneal temperature of the HZO to get a ferroelectricity with large Pr (remnant polarization) and small EC (coercive field) so that CFE can be adjusted by simply changing HZO thickness. So, an optimal matching between CFE and CMOS can be achieved to eliminate hysteresis. Also, the optimal technologies and conditions of fabricating the above ferroelectric and dielectric layers by ALD method will be investigated, and the prototype sample of the relevant MoS2 NC-FET is prepared, with greatly reducing subthreshold swing (< 60 mV/dec), ultra-low power dissipation (operation voltage below 0.5 V) and the stable NC effect and hysteresis-free operation.