EIA: Lithography for All-Vacuum Integrated Circuit Fabrication

集成电路制造仍然广泛地由制造商进行。 在设备的各个部件之间传送衬底， “洁净室”环境。 由于不可能完全控制 空气中的污染物含量， 微粒或蒸汽撞击在被处理的材料上， 从而改变器件特性并降低产品产量。 一 完成整个制造过程，包括产品转移 在真空下将导致衬底的显著减少 污染. 许多工艺步骤可以在真空下或在室温下进行。 但是一个关键的操作，即光刻，可以 没有这是目前实现全真空的一个障碍 处理.本项目的目的是研究As-S/Ag 抗蚀剂系统沉积，曝光（光学和电子束），显影， 并在真空条件下剥离， 其最终可用于全真空应用。 广泛 将使用微加工设施，包括以下设备： 蒸发和溅射，直接在晶片上步进和接触曝光， 高分辨率电子束光刻、平行板和反应离子 蚀刻，以及通过EDXA、WDS和AES的材料分析。 所得 高分辨率处理将与多次曝光兼容 在真空下的方法，并将允许取得相当大的进展， 全真空处理。

Integrated circuit fabrication is still widely carried out by transporting the substrates between individual pieces of equipment in a "cleanroom" environment. Since it is impossible to fully control the contaminant content of the air, there is ample opportunity for particulates or vapors to impinge on the materials being processed, thereby altering device characteristics and reducing product yield. A complete fabrication process, including product transfer, carried out under vacuum would result in a significant reduction of substrate contamination. Many process steps may be carried out under vacuum or at reduced pressure but one critical operation, namely lithography, may not. This is currently a barrier to the realization of all-vacuum processing. The objective of this program is to investigate As-S/Ag resist system deposition, exposure (optical and electron-beam), develop, and strip, under vacuum conditions to create a lithographical process which may ultimately be used in all-vacuum applications. Extensive microfabrication facilities will be used including equipment for evaporation and sputtering, direct step on wafer and contact exposure, high resolution e-beam lithography, parallel plate and reactive ion etching, and materials analysis by EDXA, WDS, and AES. The resulting high resolution process will be compatible with multiple exposure methods under vacuum and will allow considerable progress to be made in all-vacuum processing.