RIA: VLSI CORDIC Parallel Processor Architectures for the Singular Value Decomposition

这项研究的目标是a)开发使用复数运算的坐标旋转算法(CORDIC)；b)开发容错奇异值分解(SVD)阵列结构；以及c)开发定点CORDIC SVD处理器阵列单元的VLSI实现。首席研究员之前已经展示了高速计算机算术算法的适用性，其中包括CORDIC到实矩阵的奇异值分解的映射。在设计的CORDIC数据路径芯片的基础上，通过MOSIS服务正在制造完全定制的芯片。然后组合数据路径设计以产生完整的阵元芯片，并配置成原型阵列。对数值算法的改进将导致使用复数运算的CORDIC SVD处理器。超大规模集成电路的最新进展促进了专用处理器阵列的发展，以解决计算密集型数值算法。奇异值分解是实时信号处理和图像处理中一种重要的矩阵计算方法。这里开发的结果将导致定制的、低成本、可重新配置的高速VLSI SVD阵列，这将使许多应用程序能够实时解决。

The objectives of this research are a) to develop Coordinate Rotation Algorithms (CORDIC) using complex arithmetic; b) to develop a fault tolerant Singular Value Decomposition (SVD) array architecture; and c) to develop the VLSI implementation of a fixed-point CORDIC SVD processor-array element. The principal investigator has previously shown the applicability of high-speed computer arithmetic algorithms, which includes the mapping of CORDIC to the SVD of real matrix. Based on the CORDIC data path chips designed, fully custom CMOS chips are being fabricated through the MOSIS service. The data path designs are then combined to yield a complete array-element chip and configured into a prototype array. Improvements to numerical algorithms will lead to a CORDIC SVD processor using complex arithmetic. Recent advances in VLSI have encouraged the development of special- purpose processor arrays to solve computation-intensive numerical algorithms. SVD is an important matrix computational method for real- time signal processing and image processing. The results developed here will result in a custom, low-cost, reconfigurable, high-speed VLSI SVD array, which will allow many applications to be solvable in real time.