Functional VLSI Module-based Multiprocessor Architectures for Real-time Vision

该项目致力于通过统一接口行为来实现VLSI功能模块的系统集成。这种集成旨在使用与个别操作相对应的模块流水线来设计灵活、实时、低级的视觉系统。这项研究涉及两个方面的任务。首先，对视觉操作基准的功能模块进行了设计和表征。重点是保持控制和输入/输出要求相对于每项操作的参数变化的不变性。其次，开发了用于在通过交换节点网络连接的一组功能模块上静态映射给定操作序列的算法和相关软件。这些算法均衡了各模块的工作负载，以实现高吞吐量。根据特定于操作的输入/输出、缓冲区大小和存储器大小对各个VLSI模块进行表征，可以更真实地预测系统性能。用于视觉的多处理器体系结构可分为同构体系结构和异质体系结构。在同构体系结构中，对视觉中的各种操作进行并行性的优化开发是非常困难的，而在异质体系结构中，只实现了与手头特定视觉应用相关的一小部分低级操作。这项研究解决了开发功能模块及其集成的重要问题，以便在运行时动态地根据计算机体系结构定制视觉操作。这项研究的成功使低级和高级视觉操作的并行性得到了更好的开发。

This project focuses on system integration of VLSI functional modules by creating uniformity in their interface behavior. Such integration is aimed at designing flexible, real-time, low-level vision systems using pipelining of modules that correspond to individual operations. Two tasks are addressed in this research. First, functional modules for benchmarking vision operations are designed and characterized. Emphasis is placed on maintaining invariance in control and input/output requirements with respect to changes in the parameters of each operation. Second, algorithms and associated software for static mapping of a given sequence of operations on a set of functional modules connected through a network of switching nodes are developed. These algorithms balance the workload of the modules in order to achieve high throughput. The characterization of individual VLSI modules in terms of operation-specific input/output, buffer sizes, and memory size allows more realistic prediction of system performance. Multiprocessor architectures for vision can be classified as homogeneous architectures and heterogeneous architectures. In homogeneous architectures, exploiting parallelism optimally for the diversified operations in vision is very difficult, while in heterogeneous architectures, only a small set of low-level operations, relevant to the particular vision applications at hand, are implemented. This research addresses the important problem of developing functional modules and their integration in order to dynamically tailor vision operations to the computer architecture at run time. Success in this research allows better exploitation of parallelism for both low-level and high-level vision operations.