Implementation of a High Performance Microprocessor

修订后的项目范围是对 利用WM处理器的系统性能。 特别是 调查的目的是检查“WM的两个潜在瓶颈 系统，即内存带宽和操作系统开销-- 尤其是上下文切换”。 因为超标量和 超级流水线处理器是内存“带宽饥渴”（在 在WM处理器的情况下，最多可以有11个存储器引用， 每个处理器周期生成）--需要检查 支持这种处理器所需的存储器系统。 的指令 缓存只能消除其中一个引用，而对于vector 除了一个数据缓存之外的步幅实际上可能会减少 有效带宽 由于实现中包含大量的内部状态， WM处理器可能有（大于700字节）--成本 的上下文切换变得非常高，因为所有这些上下文必须 被保存（通常是片外的，因为大多数片上不动产是 填充有寄存器、高速缓存等）。 研究人员将探索几种设计方案， 解决这些领域中的每一个，以确定是否可行 利用WM处理器构建高性能系统。

The revised project scope is for a 12-month investigation of the SYSTEM performance utilizing a WM processor. In particular, the investigation is to examine "two potential bottlenecks of WM systems, namely memory bandwidth and operating system overhead-- especially context switching". Because superscalar and superpipelined processors are memory "bandwidth hungry" (in the case of the WM processor up to 11 memory references can be generated per processor cycle)--there is a need to examine the memory system required to support such a processor. An instruction cache can only eliminate one of these references, while for vector strides other than one a data cache may actually REDUCE the effective bandwidth. Due to the large amount of internal state which an implementation of the WM processor might have (greater than 700 bytes)--the cost of a context switch becomes very high as all of this context must be saved (typically off-chip as most of the on-chip real-estate is filled with registers, cache,...). The investigators will explore several design alternatives to address each of these areas in order to determine if it is feasible to build a high-performance SYSTEM utilizing a WM processor.