RIA: Combined Logic Synthesis and Physical Design

这项研究是在寻找有效的技术，以产生解决方案的逻辑综合和物理设计问题，同时和互动。目前正在研究两个问题领域：将逻辑综合与物理设计相结合；布尔网络的布局算法。在第一个领域，正在开发一个原型综合系统，该系统能够根据逻辑级信息和有关互连线和物理介质特性的详细数据做出综合决策。关键思想是生成捕获布局结构的布尔网络的位置。在迭代过程中维护逻辑和布局表示之间的对应关系。既支持技术独立的逻辑转换，也支持技术依赖的逻辑转换。在第二个领域，正在研究分配I/O垫或放置未映射布尔网络的节点的方法，其中节点仍然具有独立于技术的逻辑实现。能够有效捕获布尔网络结构特征并能处理不精确或近似面积、内在延迟和驱动节点的物理设计工具正在开发中。在逻辑综合和布局过程中，准确、高效的互连建模对算法的开发至关重要。

This research is on finding efficient techniques for producing solutions to logic synthesis and physical design problems both simultaneously and interactively. Two problem areas are being investigated: integrating logic synthesis with physical design; and layout algorithms for Boolean networks. In the first area, a prototype synthesis system which is capable of making synthesis decisions based on both logic level information and detailed data about the interconnecting wires and characteristics of the physical media is being developed. The key idea is to generate a placement of the Boolean network that captures the structure of the layout. The correspondence between logic and layout representations is maintained during iterations. Both technology independent and technology dependent logic transformations are accommodated. In the second area, ways to assign the I/O pads or place the nodes of an unmapped Boolean network, where the nodes still have technology independent logic realizations, are being investigated. Physical design tools which effectively capture the structural characteristics of Boolean networks and can handle nodes of inexact or approximate area, intrinsic delay and drive are being developed. Accurate and efficient modeling of interconnect during logic synthesis and layout plays a key role in the algorithm development.