Planning Meetings for the Industry/University Cooperative Research Center for Silicon Wafer Engineering and Defect Science (Si WEDS)

摘要提案：北卡罗莱纳州立大学硅晶圆缺陷工程产学研合作研究中心计划资助项目负责人：George A. Rozgonyi， NCSU项目负责人：Cheryl Cathey日期：1997年3月10日硅晶圆是构建集成电路的基础。为了在集成电路行业中具有竞争力，硅芯片制造商必须不断努力减小集成电路组件的特征尺寸。更小的特征尺寸使芯片制造商既可以制造更小的芯片，满足市场对更小电子产品的需求，又可以增加每片硅片的芯片产量，降低每片芯片的成本。为了确保高产量的高质量芯片，基础材料硅片必须尽可能避免体积和表面缺陷和缺陷。该中心将与硅晶圆制造商合作：*为晶圆制造社区的研究问题提供一个机制，由学术界识别和解决；*教育研究生和研究生成为晶圆制造研究社区的有效成员；*提供行政基础设施，以便为大规模的晶圆缺陷研究中心提供资金。该中心的研究将分为三个重点：整体缺陷和缺陷，表面缺陷和缺陷，以及计量和模拟等交叉领域。体积缺陷和缺陷推力将涉及硅晶体成核、生长、运动和湮灭的控制研究。表面缺陷推力将研究控制和设计晶圆表面性能的方法。交叉领域的推力将集中在计量发展和计量工具的基础知识。该中心将由北卡罗莱纳州立大学的George Rozgonyi博士和斯坦福大学的Ro bert Helms担任联席主任，并将包括来自亚利桑那大学、亚利桑那州立大学、南佛罗里达大学、麻省理工学院和伯克利分校的研究人员。目前有六家晶圆制造公司愿意每年支付5万美元加入该中心。凭借七所大学的研究专长，该中心将帮助硅片供应商提高硅片质量，从而使他们能够更好地满足其客户（硅片制造商）的市场需求。芯片制造商将能够生产更小、更便宜的设备，使他们在电子市场上更具竞争力。

ABSTRACT Proposal: Planning Grant for an Industry/University Cooperative Research Center for Si Wafer Defect Engineering at North Carolina State University Principal Investigator: George A. Rozgonyi, NCSU Program Officer: Cheryl Cathey Date: 10 March 1997 Silicon wafers are the foundation for building integrated circuits. In order to be competitive in the integrated circuit industry, silicon chip manufacturers must continually strive to decrease the feature size of the components of the integrated circuits. A smaller feature size enables the chip manufacturers to both make smaller chips, fulfilling the market demand for ever smaller electronics, and to increase the yield of chips per silicon wafer, decreasing the cost per chip. In order to ensure high quality chips in high yields, the base material, the silicon wafer, must be as free from bulk and surface defects and imperfections as possible. This proposed Center would work with the silicon wafer manufacturers to: * provide a mechanism for the research issues of the wafer manufacturing community to be identified and addressed by the academic community, * educate graduate and post-graduate students to become effective members of the wafer manufacturing research community, and * provide a administrative infrastructure to enable funding of a large scale wafer defect research center. The Center's research would be organized into three thrusts: bulk defects and imperfections, surface defects and imperfections, and cross-cutting areas such as metrology and simulation. The bulk defects and imperfections thrust would involve research on control of the nucleation, growth, motion and annihilation of silicon crystals. The surface defect thrust would investigate methods to control and engineer the wafer surface properties. The cross cutting areas thrust would focus on metrology development and fundamental knowledge underlying metrology tools. The Center would have Dr. George Rozgonyi of North Carolina State University and Ro bert Helms of Stanford University as co-Directors, and would involve researchers from the University of Arizona, Arizona State University, the University of South Florida, MIT, and Berkeley. There are currently six wafer manufacturing companies that are willing to pay $50,000 per year to be part of the Center. With the research expertise resident at the seven universities, this Center would aid the wafer suppliers in improving their silicon wafer quality, thus enabling them to better meet the market requirements of their customers, the silicon chip makers. The chip makers would then be able to product smaller, cheaper devices, making them more competitive in the electronics marketplace.