Operational Center for Silicon Wafer Engineering and Defect Science (Si WEDS)

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ABSTRACT EEC-9726176 Rozgoni In order to be competitive in the integrated circuit industry, silicon chip manufacturers must continually strive to decrease the feature size of the components of the integrated circuits. A smaller feature size enables the chip manufacturers to both make smaller chips, fulfilling the market demand for ever smaller electronics, and to increase the yield of chips per silicon wafer, decreasing the cost per chip. In order to ensure high quality chips in high yields, the base material, the silicon wafer, must be as free from bulk and surface defects and imperfections as possible. It is estimated that in order to meet production demands in the year 2007, defect densities in silicon wafers must be below 0.01 per cm2. It is currently not known how this goal will be reached at a cost the industry can afford. The Industry/University Cooperative Research Center for Silicon Wafer Engineering and Defect Science (Si Weds) plans to provide critical solutions to increase yield, performance and reliability of silicon materials. The center is based at North Carolina State University, and is a partnership between Arizona State University, the University of Arizona, UC Berkeley, MIT, the University of South Florida, and Stanford University.