Using Predictor Paradigms to Enhance Memory Hierarchy Performance

这项研究的重点是设计和评估硬件辅助和软件配置技术，以实现高性能系统的内存层次结构的更好利用和性能。总体目标是减少处理器和不同存储层次之间不断增加的速度差异的影响。研究方法将离线优化算法的结果与可以在存储系统中可行地实现的算法进行比较，以衡量预测触发、索引、预测机制和反馈可能带来的性能提升。这一方法将应用于三个具体问题：动态行大小选择、具有大关联性的高速缓存的替换算法以及在较低级别的存储器层次结构中的预取。

The focus of this research is the design and evaluation of hardware assists and software profiling techniques that allow better utilization and performance of the memory hierarchy of high-performance systems. The overall goal is to lessen the impact of the increasing speed discrepency between processors and the various levels of the memory hierarchy.The research methodology will compare the results of offline, optimal algorithms with algorithms that can be feasibly implemented in a memory system, to guage the performance increase possible from prediction triggering, indexing, prediction mechanisms, and feedback. This methodology will be applied to three specific problems: Dynamic line size choice, replacement algorithms for caches with large associativities, and prefetching in lower levels of the memory hierarchy.